Field effect transistor having a MIS structure and method of fabricating the same
    1.
    发明授权
    Field effect transistor having a MIS structure and method of fabricating the same 有权
    具有MIS结构的场效应晶体管及其制造方法

    公开(公告)号:US06914312B2

    公开(公告)日:2005-07-05

    申请号:US10396416

    申请日:2003-03-26

    摘要: A MIS type field effect transistor including gate dielectrics having a rare-earth metal oxynitride layer with a high dielectric constant, which can maintain good interface characteristics, can be provided. A field effect transistor according to one aspect of this invention includes a gate dielectric having a substantially crystalline rare-earth metal oxynitride layer containing one or more metals selected from rare-earth metals, oxygen, and nitrogen. The rare-earth metal oxynitride layer contacts a predetermined region of a Si semiconductor substrate, and the nitrogen exists at the interface between the rare-earth metal oxynitride layer and the Si semiconductor substrate, and in the bulk of the rare-earth metal oxynitride. The transistor further includes a gate electrode formed on the gate dielectrics and source and drain regions, one being formed at one side of the gate electrode and the other being formed at the other side of the gate electrode in the Si semiconductor substrate.

    摘要翻译: 可以提供包括能够保持良好的界面特性的具有高介电常数的稀土金属氧氮化物层的栅极电介质的MIS型场效应晶体管。 根据本发明的一个方面的场效应晶体管包括具有基本上结晶的稀土金属氧氮化物层的栅极电介质,所述稀土金属氧氮化物层含有选自稀土金属,氧和氮的一种或多种金属。 稀土金属氮氧化物层与Si半导体衬底的预定区域接触,并且氮存在于稀土金属氧氮化物层和Si半导体衬底之间的界面处,并且在大部分稀土金属氧氮化物中。 晶体管还包括形成在栅极电介质和源极和漏极区上的栅极,一个形成在栅电极的一侧,另一个形成在Si半导体衬底中的栅电极的另一侧。

    Field effect transistor and method of manufacturing the same
    2.
    发明申请
    Field effect transistor and method of manufacturing the same 失效
    场效应晶体管及其制造方法

    公开(公告)号:US20050017304A1

    公开(公告)日:2005-01-27

    申请号:US10863226

    申请日:2004-06-09

    摘要: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a convex channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.

    摘要翻译: 提供了一种场效应晶体管,包括:第一绝缘膜,形成在半导体衬底上,并且至少包括具有与半导体衬底的界面上的晶体的晶格距离不同的结晶度的金属氧化物; 形成在所述第一绝缘膜的上方的与所述半导体基板的晶格距离不同的凸状沟道区域; 源极区域和漏极区域,分别在沟道区域的侧表面上形成在第一绝缘膜的上方; 在通道区域正上方形成的第二绝缘膜; 形成在与形成有源极区域和漏极区域的沟道区域的侧面不同的沟道区域的侧面的栅极绝缘膜; 以及在与形成有源极区域和漏极区域的沟道区域的侧面不同的沟道区域的至少侧面上通过栅极绝缘膜形成的栅极电极。

    Method of manufacturing a field effect transistor comprising an insulating film including metal oxide having crystallinity and different in a lattice distance from semiconductor substrate
    4.
    发明授权
    Method of manufacturing a field effect transistor comprising an insulating film including metal oxide having crystallinity and different in a lattice distance from semiconductor substrate 有权
    制造场效应晶体管的方法,该场效应晶体管包括具有结晶度并且与半导体衬底的晶格距离不同的金属氧化物的绝缘膜

    公开(公告)号:US07538013B2

    公开(公告)日:2009-05-26

    申请号:US11472329

    申请日:2006-06-22

    IPC分类号: H01L21/20 H01L21/36

    摘要: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.

    摘要翻译: 提供了一种场效应晶体管,包括:第一绝缘膜,形成在半导体衬底上,并且至少包括具有与半导体衬底的界面上的晶体的晶格距离不同的结晶度的金属氧化物; 形成在第一绝缘膜上方的沟道区,与半导体衬底的晶格距离不同; 源极区域和漏极区域,分别在沟道区域的侧表面上形成在第一绝缘膜的上方; 在通道区域正上方形成的第二绝缘膜; 形成在与形成有源极区域和漏极区域的沟道区域的侧面不同的沟道区域的侧面的栅极绝缘膜; 以及在与形成有源极区域和漏极区域的沟道区域的侧面不同的沟道区域的至少侧面上通过栅极绝缘膜形成的栅极电极。

    Field effect transistor and method of manufacturing the same
    5.
    发明授权
    Field effect transistor and method of manufacturing the same 失效
    场效应晶体管及其制造方法

    公开(公告)号:US07091561B2

    公开(公告)日:2006-08-15

    申请号:US10863226

    申请日:2004-06-09

    摘要: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a convex channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.

    摘要翻译: 提供了一种场效应晶体管,包括:第一绝缘膜,形成在半导体衬底上,并且至少包括具有与半导体衬底的界面上的晶体的晶格距离不同的结晶度的金属氧化物; 形成在所述第一绝缘膜的上方的与所述半导体基板的晶格距离不同的凸状沟道区域; 源极区域和漏极区域,分别在沟道区域的侧表面上形成在第一绝缘膜的上方; 在通道区域正上方形成的第二绝缘膜; 形成在与形成有源极区域和漏极区域的沟道区域的侧面不同的沟道区域的侧面的栅极绝缘膜; 以及在与形成有源极区域和漏极区域的沟道区域的侧面不同的沟道区域的至少侧面上通过栅极绝缘膜形成的栅极电极。

    Semiconductor device and method for manufacturing same
    6.
    发明申请
    Semiconductor device and method for manufacturing same 审中-公开
    半导体装置及其制造方法

    公开(公告)号:US20090011537A1

    公开(公告)日:2009-01-08

    申请号:US12213918

    申请日:2008-06-26

    IPC分类号: H01L21/8234

    摘要: The present invention is to obtain an MIS transistor which allows considerable reduction in threshold fluctuation for each transistor and has a low threshold voltage. First gate electrode material for nMIS and second gate electrode material for pMIS can be mutually converted to each other, so that a process can be simplified. Such a fact that a dependency of a work function on a doping amount is small is first disclosed, so that fluctuation in threshold voltage for each transistor hardly occurs.

    摘要翻译: 本发明是为了获得允许每个晶体管的阈值波动显着降低并且具有低阈值电压的MIS晶体管。 用于nMIS的第一栅电极材料和用于pMIS的第二栅极电极材料可以相互转换,从而可以简化工艺。 首先公开了功函数对掺杂量的依赖性小的事实,因此几乎不发生各晶体管的阈值电压的波动。

    Semiconductor device including MIS transistors
    7.
    发明授权
    Semiconductor device including MIS transistors 失效
    半导体器件包括MIS晶体管

    公开(公告)号:US07405451B2

    公开(公告)日:2008-07-29

    申请号:US11020275

    申请日:2004-12-27

    IPC分类号: H01L21/8234

    摘要: The present invention is to obtain an MIS transistor which allows considerable reduction in threshold fluctuation for each transistor and has a low threshold voltage. First gate electrode material for nMIS and second gate electrode material for pMIS can be mutually converted to each other, so that a process can be simplified. Such a fact that a dependency of a work function on a doping amount is small is first disclosed, so that fluctuation in threshold voltage for each transistor hardly occurs.

    摘要翻译: 本发明是为了获得允许每个晶体管的阈值波动显着降低并且具有低阈值电压的MIS晶体管。 用于nMIS的第一栅电极材料和用于pMIS的第二栅极电极材料可以相互转换,从而可以简化工艺。 首先公开了功函数对掺杂量的依赖性小的事实,因此几乎不发生各晶体管的阈值电压的波动。