公开(公告)号：US06907555B1

公开(公告)日：2005-06-14

申请号：US09691115

申请日：2000-10-19

申请人： Yukihiro Nomura ,  Hiroyuki Fujimoto ,  Takahiro Suzuki ,  Tatsuya Kanda ,  Yasurou Matsuzaki ,  Masahiko Saitou ,  Hiroyoshi Tomita

发明人： Yukihiro Nomura ,  Hiroyuki Fujimoto ,  Takahiro Suzuki ,  Tatsuya Kanda ,  Yasurou Matsuzaki ,  Masahiko Saitou ,  Hiroyoshi Tomita

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F12/16 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  G11C29/12 ,  G11C29/44

CPC分类号： G11C29/44

摘要： The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.

摘要翻译： 本发明是一种结合在存储器件中的自检电路（BIST），其响应于来自外部的测试激活信号被激活。 当该自检电路响应于来自外部的测试激活信号（WBIZ）被激活时，它产生测试操作命令（WBI-CMD），生成测试地址（WBI-ADD），并生成测试数据（WBI- 数据）。 此外，在自检电路将测试数据写入存储单元之后，进行比较以确定从该存储单元读取的读取数据是否与写入的测试数据相同并存储信息 关于这个比较的结果。 然后将该比较结果信息输出到外部。

公开(公告)号：US06292428B1

公开(公告)日：2001-09-18

申请号：US09240007

申请日：1999-01-29

申请人： Hiroyoshi Tomita ,  Tatsuya Kanda

发明人： Hiroyoshi Tomita ,  Tatsuya Kanda

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C8/00 ,  G11C8/04 ,  G11C8/18

摘要： A semiconductor device which receives addresses in synchronism with a clock signal and receives data in synchronism with a strobe signal includes address-latch circuits, a first control circuit which selects one of the address-latch circuits in sequence in response to the clock signal, and controls the selected one of the address-latch circuits to latch a corresponding one of the addresses in response to the clock signal, and a second control circuit which selects one of the address-latch circuits in sequence in response to the strobe signal, and controls the selected one of the address-latch circuits to output a corresponding one of the addresses in response to the strobe signal.

摘要翻译： 与时钟信号同步地接收地址并与选通信号同步地接收数据的半导体器件包括地址锁存电路，响应于时钟信号依次选择地址锁存电路之一的第一控制电路，以及 控制所选择的一个地址锁存电路以响应于时钟信号锁存对应的一个地址;以及第二控制电路，其响应于选通信号依次选择一个地址锁存电路，并且控制 所选择的一个地址锁存电路响应于选通信号输出对应的一个地址。

公开(公告)号：US06813696B2

公开(公告)日：2004-11-02

申请号：US10694982

申请日：2003-10-29

申请人： Tatsuya Kanda ,  Hiroyoshi Tomita

发明人： Tatsuya Kanda ,  Hiroyoshi Tomita

IPC分类号： G06F1200

CPC分类号： G11C7/1087 ,  G11C7/1021 ,  G11C7/1039 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/222 ,  G11C29/14

摘要： The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional memory test equipment having a transfer type which transfers the data in synchronization with the rising and falling edges of the external clock. The semiconductor memory device has a write amplifier control section 14 and I/O data buffer/register 22 as a data transfer circuit corresponding to the data transfer type for the DDR type and SDR type. Also, a mode register 28 is formed to be used as a switch signal to switch the data transfer circuit to either DDR type or SDR type.

摘要翻译： 本发明涉及一种与外部时钟同步写入或读取数据的SDRAM及其控制方法，其目的在于提供一种半导体存储器件及其方法，该半导体存储器件及其方法可以容易地由具有 传输类型与外部时钟的上升沿和下降沿同步传输数据。 半导体存储器件具有写入放大器控制部分14和I / O数据缓冲器/寄存器22，作为对应于DDR类型和SDR类型的数据传输类型的数据传输电路。 此外，模式寄存器28形成为用作切换信号以将数据传输电路切换为DDR类型或SDR类型。

公开(公告)号：US6144595A

公开(公告)日：2000-11-07

申请号：US131880

申请日：1998-08-10

申请人： Osamu Hirooka ,  Hiroyoshi Tomita ,  Tatsuya Kanda

发明人： Osamu Hirooka ,  Hiroyoshi Tomita ,  Tatsuya Kanda

IPC分类号： G01R31/28 ,  G11C11/401 ,  G11C11/407 ,  G11C29/02 ,  G11C29/12 ,  G11C29/34 ,  G11C7/00

CPC分类号： G11C29/12 ,  G11C29/02

摘要： A semiconductor device outputs data from a plurality of data nodes during a normal-operation mode, and outputs a test result from at least one of the data nodes during a test-operation mode. The semiconductor device includes a plurality of data-bus lines which convey the data with respect to the data nodes, and a data-bus switch which allows only the data-bus lines corresponding to the at least one of the data nodes to be driven in a first condition of the test-operation mode, and which allows all of the data-bus lines corresponding to the data nodes to be driven in a second condition of the test-operation mode.

摘要翻译： 半导体器件在正常操作模式期间从多个数据节点输出数据，并且在测试操作模式期间从至少一个数据节点输出测试结果。 半导体器件包括相对于数据节点传送数据的多条数据总线，以及数据总线开关，该数据总线开关只允许与至少一个数据节点相对应的数据总线线驱动 测试操作模式的第一条件，并且允许在测试操作模式的第二条件下驱动对应于数据节点的所有数据总线。

公开(公告)号：US06671787B2

公开(公告)日：2003-12-30

申请号：US09264672

申请日：1999-03-09

申请人： Tatsuya Kanda ,  Hiroyoshi Tomita

发明人： Tatsuya Kanda ,  Hiroyoshi Tomita

IPC分类号： G06F1200

CPC分类号： G11C7/1087 ,  G11C7/1021 ,  G11C7/1039 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/222 ,  G11C29/14

摘要： The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional memory test equipment having a transfer type which transfers the data in synchronization with the rising and falling edges of the external clock. The semiconductor memory device has a write amplifier control section 14 and I/O data buffer/register 22 as a data transfer circuit corresponding to the data transfer type for the DDR type and SDR type. Also, a mode register 28 is formed to be used as a switch signal to switch the data transfer circuit to either DDR type or SDR type.

摘要翻译： 本发明涉及一种与外部时钟同步写入或读取数据的SDRAM及其控制方法，其目的在于提供一种半导体存储器件及其方法，该半导体存储器件及其方法可以容易地由具有 传输类型与外部时钟的上升沿和下降沿同步传输数据。 半导体存储器件具有写入放大器控制部分14和I / O数据缓冲器/寄存器22，作为对应于DDR类型和SDR类型的数据传输类型的数据传输电路。 此外，模式寄存器28形成为用作切换信号以将数据传输电路切换为DDR类型或SDR类型。

公开(公告)号：US06320819B2

公开(公告)日：2001-11-20

申请号：US09733961

申请日：2000-12-12

申请人： Hiroyoshi Tomita ,  Tatsuya Kanda

发明人： Hiroyoshi Tomita ,  Tatsuya Kanda

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C8/00 ,  G11C8/04 ,  G11C8/18

摘要： A semiconductor device which receives addresses in synchronism with a clock signal and receives data in synchronism with a strobe signal includes address-latch circuits, a first control circuit which selects one of the address-latch circuits in sequence in response to the clock signal, and controls the selected one of the address-latch circuits to latch a corresponding one of the addresses in response to the clock signal, and a second control circuit which selects one of the address-latch circuits in sequence in response to the strobe signal, and controls the selected one of the address-latch circuits to output a corresponding one of the addresses in response to the strobe signal.

公开(公告)号：US06295245B1

公开(公告)日：2001-09-25

申请号：US09385004

申请日：1999-08-27

申请人： Hiroyoshi Tomita ,  Tatsuya Kanda

发明人： Hiroyoshi Tomita ,  Tatsuya Kanda

IPC分类号： G11C1300

CPC分类号： G11C7/109 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4096

摘要： A write data input circuit for a double data rate (DDR) SDRAM acquires write data at both a rising and falling edge of a clock signal. The input circuit includes a command input buffer for receiving external commands, such as a read, write or refresh command. An external command latch circuit connected to the input buffer latches the external command in sync with a first clock signal. A decoder decodes the latched external command. A write determination circuit also receives the (undecoded) external command and generates an enable signal if the external command is a write command. A data input buffer is activated by the enable signal and receives write data. A data latch circuit latches the write data provided to the data input buffer in sync with a second clock signal.

摘要翻译： 双数据速率（DDR）SDRAM的写数据输入电路在时钟信号的上升沿和下降沿都获取写数据。 输入电路包括用于接收诸如读取，写入或刷新命令的外部命令的命令输入缓冲器。 连接到输入缓冲器的外部命令锁存电路与第一时钟信号同步地锁存外部指令。 解码器解码锁定的外部命令。 如果外部命令是写命令，则写入确定电路还接收（未解码）外部命令并产生使能信号。 数据输入缓冲器由使能信号激活并接收写入数据。 数据锁存电路与第二时钟信号同步地锁存提供给数据输入缓冲器的写入数据。

公开(公告)号：US06208582B1

公开(公告)日：2001-03-27

申请号：US09304518

申请日：1999-05-04

申请人： Tatsuya Kanda ,  Hiroyoshi Tomita

发明人： Tatsuya Kanda ,  Hiroyoshi Tomita

IPC分类号： G11C800

CPC分类号： G11C7/1096 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078

摘要： A memory device, which writes data upon receiving a write command and reads data upon receiving a read command, comprises: a data input/output circuit for inputting and outputting the data in synchronization with first and second edges of a clock; and a cell array including a plurality of memory cells which store the data are. The memory device includes two sets of data bus lines connected to the cell array via column gates, a serial/parallel converter for inputting and outputting first and second write data, and two write amplifiers for driving the two data bus lines in accordance with the first and the second write data from the serial/parallel converter. The write amplifiers are activated in a write enabled state and the write amplifier is deactivated in response to a data mask signal despite being in the write enable state. The memory device has a column decoder which selects the column gate, and is inhibited the activation in response to the data mask signal. Therefore, the write-interrupt-read operation can appropriately be performed for a memory device which is compatible with the double data rate.

摘要翻译： 一种存储装置，其在接收到写入命令时写入数据并在接收到读取命令时读取数据，包括：数据输入/输出电路，用于与时钟的第一和第二边沿同步地输入和输出数据; 并且包括存储数据的多个存储单元的单元阵列。 存储器件包括通过列门连接到单元阵列的两组数据总线，用于输入和输出第一和第二写入数据的串行/并行转换器，以及用于根据第一个数据总线驱动两个数据总线的两个写入放大器 和来自串行/并行转换器的第二个写入数据。 写入放大器在写使能状态下被激活，并且写入放大器响应于数据掩码信号被去激活，尽管处于写使能状态。 存储器件具有列解码器，其选择列门，并且响应于数据掩码信号而禁止激活。 因此，对于与双倍数据速率兼容的存储器件，可以适当地执行写入中断读取操作。

公开(公告)号：US6144614A

公开(公告)日：2000-11-07

申请号：US353364

申请日：1999-07-15

申请人： Tatsuya Kanda ,  Hiroyoshi Tomita

发明人： Tatsuya Kanda ,  Hiroyoshi Tomita

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C8/00

CPC分类号： G11C7/225 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22

摘要： A semiconductor integrated circuit includes an internal clock generating circuit generating an internal clock, and a flip-flop circuit configured so that n latch circuits are cascaded via switch circuits performing switching operations in synchronism with the internal clock where n is an integer equal to or greater than 2. An initialization control circuit is provided so that it applies, after power on, an initialization signal to the flip-flop circuit whereby a first latch circuit among the n latch circuits is initialized. The initialization control circuit causes the internal clock generating circuit to generate the internal clock during a predetermined period so that the second through nth latch circuits are sequentially initialized.

摘要翻译： 半导体集成电路包括产生内部时钟的内部时钟发生电路和触发器电路，其配置为使得n个锁存电路经由开关电路级联，所述开关电路与内部时钟同步地执行开关操作，其中n是等于或大于等于的整数 提供初始化控制电路，使得其在上电之后将触发电路的初始化信号应用于其中，从而初始化n个锁存电路中的第一锁存电路。 初始化控制电路使得内部时钟发生电路在预定周期内产生内部时钟，使得第二到第N个锁存电路被顺序地初始化。

公开(公告)号：US6115322A

公开(公告)日：2000-09-05

申请号：US266583

申请日：1999-03-11

申请人： Tatsuya Kanda ,  Hiroyoshi Tomita

发明人： Tatsuya Kanda ,  Hiroyoshi Tomita

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  H01L27/10 ,  G11C8/00

CPC分类号： G11C7/1078

摘要： A semiconductor device for accepting a data from outside in synchronization with data strobe signal. The semiconductor device includes control circuit for generating an accept-control signal which is activated in response to a write command inputted in synchronization with a clock signal and is inactivated in response to the data strobe signal in synchronization with the final data signal, and data input circuit for accepting the data signals while the accept-control signal is activated. The timing of the accept-control signal varies in accordance with the variation of the timing of the data strobe signal because the control circuit controls so as to inactivate the accept-control signal in response to the data strobe signal. Hence, inactivating of the accept-control signal is always performed within a predetermined time period after the final data signal is accepted in synchronization with the data strobe signal. As a result, the inactivating of the accept-control signal is accurately controlled in synchronization with the data strobe signal. Therefore, only necessary write-data are reliably accepted even if the timing of the data strobe signal varies.

摘要翻译： 一种用于从数据选通信号同步地接收外部数据的半导体器件。 半导体器件包括用于产生接收控制信号的控制电路，该接收控制信号响应于与时钟信号同步输入的写入命令被激活，并且响应于与最终数据信号同步的数据选通信号而被去激活，并且数据输入 在接受控制信号被激活时接收数据信号的电路。 接受控制信号的定时根据数据选通信号的定时的变化而变化，因为控制电路响应于数据选通信号而控制接收控制信号。 因此，在与数据选通信号同步地接受最终数据信号之后，总是在预定时间段内执行接受控制信号的失活。 结果，与数据选通信号同步地精确地控制接受控制信号的失活。 因此，即使数据选通信号的定时变化，只有必要的写入数据被可靠地接受。