公开(公告)号：US06653188B1

公开(公告)日：2003-11-25

申请号：US10292624

申请日：2002-11-13

申请人： Yung-Meng Huang ,  Chi-Hei Lin ,  Ching-Nan Hsiao

发明人： Yung-Meng Huang ,  Chi-Hei Lin ,  Ching-Nan Hsiao

IPC分类号： H01L21336

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： The present invention provides a method for forming a floating gate with a poly tip. The method includes the step of providing a semiconductor substrate with a gate dielectric layer formed on the semiconductor substrate. A first polysilicon layer is then formed on the gate dielectric layer. A hard mask layer is formed on the first polysilicon layer. Then, an opening is formed in the hard mask layer to expose a portion of the first polysilicon layer. Next, a poly spacer is formed in the opening. Then, the hard mask layer and the first polysilicon layer thereunder are removed to form the floating gate.

摘要翻译： 本发明提供了一种用于形成具有多个尖端的浮动栅极的方法。 该方法包括为半导体衬底提供形成在半导体衬底上的栅介质层的步骤。 然后在栅极电介质层上形成第一多晶硅层。 在第一多晶硅层上形成硬掩模层。 然后，在硬掩模层中形成开口以露出第一多晶硅层的一部分。 接下来，在开口中形成多个间隔物。 然后，去除硬掩模层和其下的第一多晶硅层以形成浮栅。

公开(公告)号：US20050032308A1

公开(公告)日：2005-02-10

申请号：US10775307

申请日：2004-02-10

申请人： Ching-Nan Hsiao ,  Chao-Sung Lai ,  Yung-Meng Huang

发明人： Ching-Nan Hsiao ,  Chao-Sung Lai ,  Yung-Meng Huang

IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A multi-bit vertical memory cell and method of fabricating the same. The multi-bit vertical memory cell comprises a semiconductor substrate with a trench, a plurality of bit lines formed therein near its surface and the bottom trench respectively, a plurality of bit line insulating layers over each bit line, a silicon rich oxide layer conformably formed on the sidewall of the trench and the surface of the surface of the bit line insulating layer, and a word line over the silicon rich oxide layer, and the trench is filled with the word line.

摘要翻译： 一种多位垂直存储单元及其制造方法。 多位垂直存储单元包括具有沟槽的半导体衬底，分别在其表面附近形成的多个位线和底部沟槽，每个位线上的多个位线绝缘层，顺应地形成的富硅氧化物层 在沟槽的侧壁和位线绝缘层的表面的表面以及位于富硅氧化物层上的字线，并且沟槽被字线填充。

公开(公告)号：US20050087823A1

公开(公告)日：2005-04-28

申请号：US10994018

申请日：2004-11-19

申请人： Ching-Nan Hsiao ,  Chao-Sung Lai ,  Yung-Meng Huang ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Chao-Sung Lai ,  Yung-Meng Huang ,  Ying-Cheng Chuang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7923

摘要： A read-only memory cell (ROM) and a fabrication method thereof. The cell comprises a substrate, a plurality of bit lines, a plurality of bit line oxides, a gate dielectric layer and a word line. The bit lines are formed near the surface of the substrate. The bit line oxides are disposed over the bit lines. The gate dielectric layer is disposed over the substrate between the bit lines and further comprises a silicon-rich oxide layer. The word line is disposed over the bit line oxides and the gate dielectric layer.

摘要翻译： 只读存储单元（ROM）及其制造方法。 电池包括衬底，多个位线，多个位线氧化物，栅极电介质层和字线。 在基板的表面附近形成位线。 位线氧化物位于位线之上。 栅介电层设置在位线之间的衬底上，并且还包括富硅氧化物层。 字线设置在位线氧化物和栅极电介质层之上。

公开(公告)号：US06451654B1

公开(公告)日：2002-09-17

申请号：US10029429

申请日：2001-12-18

申请人： Chi-Hui Lin ,  Chung-Lin Huang ,  Yung-Meng Huang

发明人： Chi-Hui Lin ,  Chung-Lin Huang ,  Yung-Meng Huang

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： The present invention provides a process for fabricating a self-aligned split gate flash memory. First, a patterned gate oxide layer, a first patterned polysilicon layer, and a first patterned mask layer are successively formed on a semiconductor substrate, and a first insulating spacer is formed on their sidewalls. Then, shallow trench isolation (STI) is formed in the substrate using the first patterned mask layer and the first insulating spacer as a mask. Then, the first patterned mask layer and a part of the first insulating spacer are removed to expose the first patterned polysilicon layer. A floating gate region is defined on the first patterned polysilicon layer, and the surface of the first polysilicon layer in the floating gate region is selectively oxidized to form polysilicon oxide layer. Then, the polysilicon oxide layer is used as a mask to remove the underlying first polysilicon layer in a self-aligned manner to form a floating gate. Finally, an intergate insulating layer and a second patterned polysilicon layer as a control gate are succesively formed on the polysilicon oxide layer. The present invention forms a floating gate in a self-aligned manner, which can decreases critical dimension. When an oxidation process is conducted to form the above polysilicon oxide layer, the nitride liner layer and the insulating spacer formed in the trench protect the sides of floating gate from oxygen invasion. This prevents the line width of floating gate from size reduction. Current leakage is also be avoided.

摘要翻译： 本发明提供一种用于制造自对准分离栅闪存的方法。 首先，在半导体衬底上依次形成图案化栅极氧化物层，第一图案化多晶硅层和第一图案化掩模层，并且在其侧壁上形成第一绝缘间隔物。 然后，使用第一图案化掩模层和第一绝缘间隔物作为掩模在衬底中形成浅沟槽隔离（STI）。 然后，去除第一图案化掩模层和第一绝缘间隔物的一部分以露出第一图案化多晶硅层。 在第一图案化多晶硅层上限定浮栅区域，并且浮栅区域中的第一多晶硅层的表面被选择性地氧化以形成多晶硅氧化物层。 然后，将多晶硅氧化物层用作掩模，以自对准的方式去除下面的第一多晶硅层以形成浮动栅极。 最后，在多晶硅氧化物层上连续地形成作为控制栅极的栅极绝缘层和第二图案化多晶硅层。 本发明以自对准的方式形成浮动栅极，这可以降低临界尺寸。 当进行氧化处理以形成上述多晶硅氧化物层时，形成在沟槽中的氮化物衬垫层和绝缘衬垫保护浮动栅极的侧面免受氧气侵入。 这样可以防止浮动栅极的线宽缩小。 电流泄漏也被避免。

公开(公告)号：US07948027B1

公开(公告)日：2011-05-24

申请号：US12635662

申请日：2009-12-10

申请人： Shing-Hwa Renn ,  Cheng-Chih Huang ,  Yung-Meng Huang

发明人： Shing-Hwa Renn ,  Cheng-Chih Huang ,  Yung-Meng Huang

IPC分类号： H01L29/76

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10885

摘要： An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.

摘要翻译： 一种嵌入式位线结构，其中，衬底包括具有原始顶表面的绝缘体层和在绝缘体层的原始顶表面上的半导体层，并且位线沿着一侧设置在沟槽的下部 的活跃区域。 位线包括第一部分和第二部分。 第一部分位于绝缘体层内并且位于绝缘体层的原始顶表面下方。 第二部分设置在第一部分上以电连接有源区的半导体层。 绝缘体衬垫设置在位线的第一部分上，位于位线的第二部分与衬底的半导体层之间，与激活区域相反以进行隔离。 STI设置在沟槽内以围绕有源区域进行隔离。

公开(公告)号：US06699754B2

公开(公告)日：2004-03-02

申请号：US10302285

申请日：2002-11-22

申请人： Yung-Meng Huang

发明人： Yung-Meng Huang

IPC分类号： H01L218242

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  Y10S438/962 ,  Y10S438/979

摘要： A flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, and a source/drain region. The floating gate, disposed over the substrate and insulated from the substrate, has a plurality of hut structures. The control gate is disposed over the floating gate and insulated from the floating gate. The source/drain region is formed in the substrate. This invention further includes a method of fabricating a flash memory cell. First, a polysilicon layer and a germanium layer are successively formed over a substrate and insulated from the substrate. Subsequently, the substrate is annealed to form a germanium layer having a plurality of hut structures on the polysilicon layer to serve as a floating gate with the polysilicon layer. Next, a control gate is formed over the floating gate and insulated from the floating gate. Finally, a source/drain region is formed in the substrate.

公开(公告)号：US20110140196A1

公开(公告)日：2011-06-16

申请号：US12635662

申请日：2009-12-10

申请人： Shing-Hwa Renn ,  Cheng-Chih Huang ,  Yung-Meng Huang

发明人： Shing-Hwa Renn ,  Cheng-Chih Huang ,  Yung-Meng Huang

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10885

摘要： An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.

摘要翻译： 一种嵌入式位线结构，其中，衬底包括具有原始顶表面的绝缘体层和在绝缘体层的原始顶表面上的半导体层，并且位线沿着一侧设置在沟槽的下部 的活跃区域。 位线包括第一部分和第二部分。 第一部分位于绝缘体层内并且位于绝缘体层的原始顶表面下方。 第二部分设置在第一部分上以电连接有源区的半导体层。 绝缘体衬垫设置在位线的第一部分上，位于位线的第二部分与衬底的半导体层之间，与激活区域相反以进行隔离。 STI设置在沟槽内以围绕有源区域进行隔离。

公开(公告)号：US06916748B2

公开(公告)日：2005-07-12

申请号：US10302488

申请日：2002-11-22

申请人： Yung-Meng Huang

发明人： Yung-Meng Huang

IPC分类号： H01J9/02 ,  H01L21/302 ,  H01L21/461 ,  H01L31/12

CPC分类号： H01J9/025

摘要： A method of forming emitter tips on a field emission display. A conductive layer is formed on a substrate, and then a photoresist layer is formed on the conductive layer wherein the photoresist layer has at least a pattern for defining predetermined areas of the emitter tips. Next, using plasma etching with the pattern of the photoresist layer as a mask, the conductive layer is etched to become a plurality of emitter stages. The etching rate of the conductive layer is greater than the etching rate of the photoresist layer. Finally, continuous use of plasma etching with an increased vertical-etching rate etches the lateral sidewalls of the emitter stages, thus shaping them as emitter tips.

摘要翻译： 一种在场发射显示器上形成发射极尖端的方法。 在衬底上形成导电层，然后在导电层上形成光致抗蚀剂层，其中光刻胶层至少具有用于限定发射极尖端的预定区域的图案。 接下来，使用具有光致抗蚀剂层的图案的等离子体蚀刻作为掩模，将导电层蚀刻成多个发射极级。 导电层的蚀刻速率大于光致抗蚀剂层的蚀刻速率。 最后，连续使用具有增加的垂直蚀刻速率的等离子体蚀刻蚀刻发射极级的侧壁，从而将它们形成为发射极尖端。

公开(公告)号：US06900099B2

公开(公告)日：2005-05-31

申请号：US10740305

申请日：2003-12-18

申请人： Yung-Meng Huang

发明人： Yung-Meng Huang

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  Y10S438/962 ,  Y10S438/979

摘要： A flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, and a source/drain region. The floating gate, disposed over the substrate and insulated from the substrate, has a plurality of hut structures. The control gate is disposed over the floating gate and insulated from the floating gate. The source/drain region is formed in the substrate. This invention further includes a method of fabricating a flash memory cell. First, a polysilicon layer and a germanium layer are successively formed over a substrate and insulated from the substrate. Subsequently, the substrate is annealed to form a germanium layer having a plurality of hut structures on the polysilicon layer to serve as a floating gate with the polysilicon layer. Next, a control gate is formed over the floating gate and insulated from the floating gate. Finally, a source/drain region is formed in the substrate.

摘要翻译： 闪存单元。 存储单元包括衬底，浮置栅极，控制栅极和源极/漏极区域。 设置在基板上并与基板绝缘的浮动栅极具有多个小屋结构。 控制栅极设置在浮动栅极上并与浮动栅极绝缘。 源极/漏极区域形成在衬底中。 本发明还包括制造闪存单元的方法。 首先，在基板上依次形成多晶硅层和锗层，并与基板绝缘。 随后，将基板退火以在多晶硅层上形成具有多个小室结构的锗层，以用作具有多晶硅层的浮动栅极。 接下来，控制栅极形成在浮动栅极上并与浮动栅极绝缘。 最后，在衬底中形成源/漏区。