公开(公告)号：US06824452B1

公开(公告)日：2004-11-30

申请号：US10605425

申请日：2003-09-30

申请人： Yung-Tai Hung ,  Yuhturng Liu ,  Hsueh-Hao Shih ,  Kuang-Chao Chen

发明人： Yung-Tai Hung ,  Yuhturng Liu ,  Hsueh-Hao Shih ,  Kuang-Chao Chen

IPC分类号： B24B100

CPC分类号： B24B37/24 ,  B24B37/042 ,  B24D3/32 ,  B24D13/147

摘要： A chemical mechanical polishing to polish a substrate having a layer to be polished thereon is described. A pre-polishing process is performed using a softer polishing pad to remove partially raised parts of the layer to be polished before conducting a polishing process using a harder polishing pad. Since the first polishing pad is flexible, porous and with low density, the first polishing pad can be deformed to increase contact areas between the first polishing pad and the raised part of the layer to be polished, and the abrasives are embedded easily in holes of the surface of the first polishing pad. Ultimately, the layer to be polished can be polished directly during the pre-polishing process. Therefore, the processing time is reduced, the consumption of the slurry is decreased and the process cost can be cut down substantially.

摘要翻译： 描述了对具有待抛光层的基板进行化学机械抛光。 在使用更硬的抛光垫进行抛光处理之前，使用较软的抛光垫进行预抛光工艺以去除待抛光层的部分凸起部分。 由于第一抛光垫是柔性的，多孔的并且具有低密度，所以第一抛光垫可以变形以增加第一抛光垫与被抛光层的凸起部分之间的接触面积，并且磨料易于嵌入到 第一抛光垫的表面。 最终，抛光过程中可以直接抛光抛光层。 因此，处理时间缩短，浆料的消耗量减少，工序成本大幅降低。

公开(公告)号：US20050084990A1

公开(公告)日：2005-04-21

申请号：US10685484

申请日：2003-10-16

申请人： Yuh-Turng Liu ,  Kuang-Chao Chen ,  Hsueh-Hao Shih ,  Yun-Chi Yang ,  Yung-Tai Hung

发明人： Yuh-Turng Liu ,  Kuang-Chao Chen ,  Hsueh-Hao Shih ,  Yun-Chi Yang ,  Yung-Tai Hung

IPC分类号： G01R31/26 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/44 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/66 ,  H01L21/768

CPC分类号： H01L21/31053 ,  H01L21/76819

摘要： A method of manufacturing a semiconductor device that comprises the steps of providing a semiconductor wafer including a patterned layer, forming a first insulating layer over the patterned layer of the semiconductor wafer, the first insulating layer including a first index of refraction, forming a second insulating layer over the first insulating layer, the second insulating layer including a second index of refraction smaller than the first index of refraction, removing the second insulating layer by a planarizing process, and detecting a change in index of refraction during the planarizing process.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：提供包括图案化层的半导体晶片，在半导体晶片的图案化层上形成第一绝缘层，第一绝缘层包括第一折射率，形成第二绝缘层 第二绝缘层包括小于第一折射率的第二折射率，通过平坦化处理去除第二绝缘层，并且在平坦化处理期间检测折射率的变化。

公开(公告)号：US06887757B2

公开(公告)日：2005-05-03

申请号：US10249867

申请日：2003-05-14

申请人： Kuang-Chao Chen ,  Hsueh-Hao Shih ,  Ling-Wuu Yang

发明人： Kuang-Chao Chen ,  Hsueh-Hao Shih ,  Ling-Wuu Yang

IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L27/105

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A method of fabricating a flash memory device is provided. First, a substrate partitioned into a memory cell region and a peripheral circuit region is provided. A tunnel dielectric layer is formed over the memory cell region and a liner layer is formed over the peripheral circuit region. Thereafter, a patterned gate conductive layer is formed over the substrate. An inter-gate dielectric layer and a passivation layer are sequentially formed over the substrate. The passivation layer, the inter-gate dielectric layer, the gate conductive layer and the liner layer over the peripheral circuit region are removed. A gate dielectric layer is formed over the peripheral circuit region while the passivation layer over the memory cell region is converted into an oxide layer. Another conductive layer is formed over the substrate. The conductive layer, the oxide layer, the inter-gate dielectric layer and the gate conductive layer over the memory cell region are patterned to form a memory gate. The second conductive layer over the peripheral circuit region is similarly patterned to form a gate.

摘要翻译： 提供一种制造闪速存储器件的方法。 首先，提供分割为存储单元区域和外围电路区域的基板。 在存储单元区域上形成隧道介电层，并在外围电路区域上形成衬垫层。 此后，在衬底上形成图案化的栅极导电层。 栅极间电介质层和钝化层依次形成在衬底上。 外围电路区域上的钝化层，栅极间电介质层，栅极导电层和衬垫层被去除。 在外围电路区域上形成栅极电介质层，同时将存储单元区域上的钝化层转换成氧化物层。 在衬底上形成另一导电层。 将存储单元区域上的导电层，氧化物层，栅极间电介质层和栅极导电层图案化以形成存储栅极。 外围电路区域上的第二导电层类似地构图形成栅极。

公开(公告)号：US06911374B2

公开(公告)日：2005-06-28

申请号：US10604615

申请日：2003-08-05

申请人： Chin Hsiang Lin ,  Chin-Wei Liao ,  Hsueh-Hao Shih ,  Kuang-Chao Chen

发明人： Chin Hsiang Lin ,  Chin-Wei Liao ,  Hsueh-Hao Shih ,  Kuang-Chao Chen

IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76232 ,  H01L21/31111 ,  H01L21/31155

摘要： A fabrication method for a shallow trench isolation region is described. A part of the trench is filled with a first insulation layer, followed by performing a surface treatment process to form a surface treated layer on the surface of a part of the first insulation layer. The surface treated layer is then removed, followed by forming a second insulation layer on the first insulation layer and filling the trench to form a shallow trench isolation region. Since a part of the trench is first filled with the first insulation layer, followed by removing a portion of the first insulation layer, the aspect ratio of the trench is lower before the filling of the second insulation in the trench. The adverse result, such as, void formation in the shallow trench isolation region due to a high aspect ratio, is thus prevented.

摘要翻译： 描述了浅沟槽隔离区域的制造方法。 沟槽的一部分填充有第一绝缘层，随后进行表面处理工艺以在第一绝缘层的一部分的表面上形成表面处理层。 然后去除表面处理层，随后在第一绝缘层上形成第二绝缘层，并填充沟槽以形成浅沟槽隔离区域。 由于沟槽的一部分首先填充有第一绝缘层，接着除去第一绝缘层的一部分，沟槽的纵横比在填充沟槽中的第二绝缘体之前较低。 因此防止由于高纵横比而导致浅沟槽隔离区域中的空隙形成的不良结果。

公开(公告)号：US20050009337A1

公开(公告)日：2005-01-13

申请号：US10604835

申请日：2003-08-21

申请人： Hung-Wei Liu ,  Kuang-Chao Chen ,  Hsueh-Hao Shih

发明人： Hung-Wei Liu ,  Kuang-Chao Chen ,  Hsueh-Hao Shih

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/44

CPC分类号： H01L21/28518

摘要： A method of forming a suicide layer is described. A silicon layer is provided. Ions are introduced in the silicon layer. A metal layer is formed on the silicon layer. An annealing process is performed so that the silicon layer reacts with the metal layer to form the metal silicide layer. Thereafter, the unreacted metal layer is removed. The uniformity of the grain size and the grain distribution of the metal silicide layer are improved by introducing the ions in the silicon layer before performing the annealing process, so that sheet resistance of the metal silicide layer is reduced.

摘要翻译： 描述了形成硅化物层的方法。 提供硅层。 硅在硅层中引入了离子。 在硅层上形成金属层。 执行退火处理，使得硅层与金属层反应以形成金属硅化物层。 之后，除去未反应的金属层。 在进行退火处理之前，通过在硅层中引入离子来改善金属硅化物层的晶粒尺寸和晶粒分布的均匀性，从而降低金属硅化物层的薄层电阻。

公开(公告)号：US06677255B1

公开(公告)日：2004-01-13

申请号：US10230328

申请日：2002-08-29

申请人： Hsueh-Hao Shih ,  Kuang-Chao Chen

发明人： Hsueh-Hao Shih ,  Kuang-Chao Chen

IPC分类号： H01L2131

CPC分类号： H01L29/6653 ,  H01L21/28273 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/66825 ,  Y10S438/954

摘要： A method of manufacturing a semiconductor device including providing a first layer, forming a layer of stacked oxide-nitride-oxide layer over the first layer, depositing a first silicon layer over the layer of stacked oxide-nitride-oxide layer, providing a layer of photoresist over the first silicon layer, patterning and defining the photoresist layer, etching the first silicon layer and stacked oxide-nitride-oxide layer unmasked by the photoresist, removing the photoresist layer, providing a cleaning solution to the stacked oxide-nitride-oxide layer with the first silicon layer as a mask, and depositing a second layer of polysilicon over the first silicon layer to form a combined silicon layer.

摘要翻译： 一种制造半导体器件的方法，包括提供第一层，在第一层上形成层叠的氧化物 - 氮化物 - 氧化物层的层，在层叠的氧化物 - 氮化物 - 氧化物层的层上沉积第一硅层，提供层 在第一硅层上的光致抗蚀剂，图案化和限定光致抗蚀剂层，蚀刻由光致抗蚀剂未被掩模的第一硅层和层叠的氧化物 - 氮化物 - 氧化物层，去除光致抗蚀剂层，为层叠的氧化物 - 氮化物 - 氧化物层提供清洁溶液 以第一硅层作为掩模，并在第一硅层上沉积第二层多晶硅以形成组合的硅层。

公开(公告)号：US06248644B1

公开(公告)日：2001-06-19

申请号：US09301210

申请日：1999-04-28

申请人： Gwo-Shii Yang ,  Hsueh-Hao Shih ,  Chih-Chien Liu ,  Tri-Rung Yew

发明人： Gwo-Shii Yang ,  Hsueh-Hao Shih ,  Chih-Chien Liu ,  Tri-Rung Yew

IPC分类号： H01L2176

CPC分类号： H01L21/76235

摘要： A method of fabricating a shallow trench isolation structure is described. A preserve layer is formed on a substrate. A trench is formed in the substrate and the preserve layer. An oxide layer is formed over the substrate to fill the trench. A wet densification step is performed in a moist environment. A planarization step is performed until the preserve layer is exposed. A shallow trench isolation structure is formed.

摘要翻译： 描述了制造浅沟槽隔离结构的方法。 在基板上形成保护层。 在衬底和保护层中形成沟槽。 在衬底上形成氧化物层以填充沟槽。 在潮湿的环境中进行湿致密化步骤。 进行平坦化步骤直到保护层被暴露。 形成浅沟槽隔离结构。

公开(公告)号：US20060134863A1

公开(公告)日：2006-06-22

申请号：US11015154

申请日：2004-12-17

申请人： Hung-Wei Liu ,  Hsueh-Hao Shih ,  Szu-Yu Wang

发明人： Hung-Wei Liu ,  Hsueh-Hao Shih ,  Szu-Yu Wang

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L21/28525 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28518 ,  H01L29/42324 ,  H01L29/4234

摘要： The present invention is directed to forming memory wordlines having a relatively lower sheet resistance. In one embodiment, a first poly-Si portion is deposited on a semiconductor substrate using a first precursor gas flow rate. A second poly-Si portion is deposited using a second precursor gas flow rate, where the second precursor flow rate higher than the first precursor gas flow rate. A tungsten silicide layer is deposited using silane gas. Wordlines are formed in trenches from poly-Si and WSix. A gate electrode is implanted.

摘要翻译： 本发明涉及形成具有相对较低的薄层电阻的记忆字线。 在一个实施例中，使用第一前体气体流速将第一多晶硅部分沉积在半导体衬底上。 使用第二前体气体流速沉积第二多晶硅部分，其中第二前体流速高于第一前体气体流速。 使用硅烷气体沉积硅化钨层。 字沟形成于poly-Si和WSix的沟槽中。 植入栅电极。

公开(公告)号：USRE40113E1

公开(公告)日：2008-02-26

申请号：US10246826

申请日：2002-09-17

申请人： Yu-Shan Tai ,  H. T. Yang ,  Hsueh-Hao Shih ,  Kuen-Chu Chen

发明人： Yu-Shan Tai ,  H. T. Yang ,  Hsueh-Hao Shih ,  Kuen-Chu Chen

IPC分类号： H01L21/336 ,  H01L21/31

CPC分类号： H01L21/28185 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02337 ,  H01L21/28211 ,  H01L21/31675

摘要： A method for fabricating gate oxide includes a dilute wet oxidation process with additional nitrogen and moisture and an annealing process with a nitrogen base gas, wherein the volume of additional nitrogen is about 6-12 6-20 times of the volume of the additional moisture. The method according to the invention improves the electrical quality of the gate oxide by raising the Qbd and by reducing the leakage current of the gate oxide.

摘要翻译： 一种制造栅极氧化物的方法包括具有额外氮和水分的稀释湿式氧化方法以及与氮气气体的退火处理，其中附加氮的体积约为<△delete-start id =“DEL-S-00001”的日期 =“20080226”？> 6-12 <？delete-end id =“DEL-S-00001”？> <？insert-start id =“INS-S-00001”date =“20080226”？> 6-20 < ？insert-end id =“INS-S-00001”？>附加水分体积的倍数。 根据本发明的方法通过提高栅极氧化物的栅极氧化物的电气质量和通过减小栅极氧化物的漏电流来改善电气质量。

公开(公告)号：US06319861B1

公开(公告)日：2001-11-20

申请号：US09562529

申请日：2000-05-02

申请人： Hsueh-Hao Shih ,  Alan Cheng ,  Juan-Yuan Wu

发明人： Hsueh-Hao Shih ,  Alan Cheng ,  Juan-Yuan Wu

IPC分类号： H01L2131

CPC分类号： H01L21/02046 ,  H01L21/02049

摘要： A method for improving the quality of a deposited layer over a silicon substrate in a selective deposition where the silicon substrate has a native oxide layer thereon. A plasma reaction using a halogen compound as a reactive agent is performed so that the native oxide layer is transformed into a silicon halide layer and then removed at low pressure. A layer of the desired material is formed over the native oxide free silicon substrate surface by selective deposition.

摘要翻译： 一种用于在选择性沉积中提高硅衬底上的沉积层的质量的方法，其中硅衬底上具有自然氧化物层。 进行使用卤素化合物作为反应剂的等离子体反应，使得天然氧化物层转变成卤化硅层，然后在低压下除去。 通过选择性沉积在所述自然无氧化物硅衬底表面上形成所需材料层。