公开(公告)号：US20060214268A1

公开(公告)日：2006-09-28

申请号：US11385762

申请日：2006-03-22

申请人： Yusuke Maeyama ,  Koichi Nishikawa ,  Yusuke Fukuda ,  Masaaki Shimizu ,  Masashi Satoh ,  Hiroaki Iwakuro ,  Kenichi Nonaka

发明人： Yusuke Maeyama ,  Koichi Nishikawa ,  Yusuke Fukuda ,  Masaaki Shimizu ,  Masashi Satoh ,  Hiroaki Iwakuro ,  Kenichi Nonaka

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L21/046 ,  H01L21/0485 ,  H01L29/6606 ,  H01L29/66068

摘要： A semiconductor device includes: a passivation film; a first semiconductor layer that has a first main component of 4H—SiC of a first conductivity type; and a second semiconductor layer that has a second main component of 4H—SiC of a second conductivity type. The second semiconductor layer has a pn-junction with the first semiconductor layer. The pn-junction has a junction edge. The first and second semiconductor layers further include a local area that includes the junction edge. The local area has a first principal plane that interfaces with the passivation film. A normal to the first principal plane tilts by a first tilt angle in a range of 25 degrees to 45 degrees from a first axis of [0001] or [000-1] toward a second axis of .

摘要翻译： 一种半导体器件包括：钝化膜; 具有第一导电类型的4H-SiC的第一主要成分的第一半导体层; 以及具有第二导电类型的4H-SiC的第二主要成分的第二半导体层。 第二半导体层具有与第一半导体层的pn结。 pn结具有接合边缘。 第一和第二半导体层还包括包括接合边缘的局部区域。 局部区域具有与钝化膜相接的第一主平面。 第一主平面的法线在从[0001]或[000-1]的第一轴朝向<01-10>的第二轴的25度至45度的范围内倾斜第一倾斜角。

公开(公告)号：US07544552B2

公开(公告)日：2009-06-09

申请号：US11386661

申请日：2006-03-23

申请人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito ,  Hiroaki Iwakuro ,  Masaaki Shimizu ,  Yusuke Fukuda ,  Koichi Nishikawa ,  Yusuke Maeyama

发明人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito ,  Hiroaki Iwakuro ,  Masaaki Shimizu ,  Yusuke Fukuda ,  Koichi Nishikawa ,  Yusuke Maeyama

IPC分类号： H01L21/337 ,  H01L29/772 ,  H01L21/339 ,  H01L21/338 ,  H01L29/768 ,  H01L29/78

CPC分类号： H01L29/7722

摘要： A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.

摘要翻译： 一种用于制造具有形成第一高电阻层的步骤的接合半导体器件的制造方法，形成沟道掺杂层的步骤，用于形成第二高电阻层的步骤，形成低电阻的步骤 作为源极区域的第一导电类型的层，用于对第二高电阻层和低电阻层的中间深度进行部分蚀刻的步骤，用于在第二高电阻层和低电阻层的蚀刻部分的下方形成栅极区域的步骤 蚀刻步骤，以及在栅极区域和源极区域之间的区域的表面上形成保护膜的步骤。 在表面中使用相对较低能量的离子注入，预先将蚀刻的源极区域的下表面和沟道掺杂层的上表面之间的高度形成为栅极区域。

公开(公告)号：US20060216879A1

公开(公告)日：2006-09-28

申请号：US11386661

申请日：2006-03-23

申请人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito ,  Hiroaki Iwakuro ,  Masaaki Shimizu ,  Yusuke Fukuda ,  Koichi Nishikawa ,  Yusuke Maeyama

发明人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito ,  Hiroaki Iwakuro ,  Masaaki Shimizu ,  Yusuke Fukuda ,  Koichi Nishikawa ,  Yusuke Maeyama

IPC分类号： H01L21/337

CPC分类号： H01L29/7722

摘要： A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.

公开(公告)号：US20070032002A1

公开(公告)日：2007-02-08

申请号：US11496627

申请日：2006-08-01

申请人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Hiroaki Iwakuro ,  Koichi Nishikawa ,  Masaaki Shimizu ,  Yusuke Fukuda

发明人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Hiroaki Iwakuro ,  Koichi Nishikawa ,  Masaaki Shimizu ,  Yusuke Fukuda

IPC分类号： H01L21/337 ,  H01L21/425 ,  H01L21/265 ,  H01L21/336 ,  H01L21/00

CPC分类号： H01L29/8083 ,  H01L21/0465 ,  H01L21/266 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068 ,  Y10S438/931

摘要： A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.

摘要翻译： 公开了一种用于制造离子注入掩模的方法，其包括以下步骤：在半导体衬底的整个表面上形成氧化膜作为保护膜; 在氧化膜上形成薄金属膜; 以及在所述薄金属膜上形成由离子抑制金属构成的离子抑制层。 所获得的离子注入掩模用于形成更深的选择性导电区域。

公开(公告)号：US08105927B2

公开(公告)日：2012-01-31

申请号：US12716916

申请日：2010-03-03

申请人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Hiroaki Iwakuro ,  Koichi Nishikawa ,  Masaaki Shimizu ,  Yusuke Fukuda

发明人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Hiroaki Iwakuro ,  Koichi Nishikawa ,  Masaaki Shimizu ,  Yusuke Fukuda

IPC分类号： H01L21/425

CPC分类号： H01L29/8083 ,  H01L21/0465 ,  H01L21/266 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068 ,  Y10S438/931

摘要： A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.

摘要翻译： 公开了一种用于制造离子注入掩模的方法，其包括以下步骤：在半导体衬底的整个表面上形成氧化膜作为保护膜; 在氧化膜上形成薄金属膜; 以及在所述薄金属膜上形成由离子抑制金属构成的离子抑制层。 所获得的离子注入掩模用于形成更深的选择性导电区域。

公开(公告)号：US07709862B2

公开(公告)日：2010-05-04

申请号：US11496627

申请日：2006-08-01

申请人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Hiroaki Iwakuro ,  Koichi Nishikawa ,  Masaaki Shimizu ,  Yusuke Fukuda

发明人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Hiroaki Iwakuro ,  Koichi Nishikawa ,  Masaaki Shimizu ,  Yusuke Fukuda

IPC分类号： H01L29/76

CPC分类号： H01L29/8083 ,  H01L21/0465 ,  H01L21/266 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068 ,  Y10S438/931

摘要： A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.

摘要翻译： 公开了一种用于制造离子注入掩模的方法，其包括以下步骤：在半导体衬底的整个表面上形成氧化膜作为保护膜; 在氧化膜上形成薄金属膜; 以及在所述薄金属膜上形成由离子抑制金属构成的离子抑制层。 所获得的离子注入掩模用于形成更深的选择性导电区域。

公开(公告)号：US08703626B2

公开(公告)日：2014-04-22

申请号：US11889403

申请日：2007-08-13

申请人： Koichi Nishikawa ,  Masaaki Shimizu ,  Kenichi Nonaka ,  Seiichi Yokoyama ,  Hideki Hashimoto

发明人： Koichi Nishikawa ,  Masaaki Shimizu ,  Kenichi Nonaka ,  Seiichi Yokoyama ,  Hideki Hashimoto

IPC分类号： H01L21/00

CPC分类号： H01L21/67115 ,  H01L21/67103 ,  H01L21/68721 ,  H01L29/1608 ,  H01L29/6606 ,  Y10T29/49117 ,  Y10T29/49124

摘要： A method of manufacturing a semiconductor device, includes increasing adherence between a susceptor as a heating element, and a semiconductor substrate disposed on the susceptor, by using an adherence increasing mechanism, or increasing heat transmitted to a semiconductor substrate, which is disposed on a susceptor as a heating element, by using a transmitted-heat increasing mechanism; and heating the semiconductor substrate to have a predetermined temperature by heating the susceptor. The adherence increasing mechanism may include the susceptor and one of a heavy-weight stone disposed on the semiconductor substrate, a cap disposed on the semiconductor substrate and engaged with the susceptor, and an adhesive layer provided between the susceptor and the semiconductor substrate. The transmitted-heat increasing mechanism may include the susceptor and small pieces which are disposed on the semiconductor substrate and have radiated-light absorption ability. The susceptor may hold a plurality of the semiconductor substrates in a stacked form.

摘要翻译： 一种制造半导体器件的方法包括通过使用附着增加机构增加作为加热元件的基座和设置在基座上的半导体基板之间的粘附性，或者增加传输到半导体基板的热量，该半导体基板设置在基座 作为加热元件，通过使用透热增加机构; 并且通过加热所述基座来加热所述半导体衬底以具有预定温度。 附着增加机构可以包括基座和设置在半导体衬底上的重量级的石块之一，设置在半导体衬底上并与基座接合的帽以及设置在基座和半导体衬底之间的粘合剂层。 透热增加机构可以包括设置在半导体衬底上并具有辐射光吸收能力的基座和小片。 基座可以以堆叠的形式保持多个半导体衬底。

公开(公告)号：US20080052901A1

公开(公告)日：2008-03-06

申请号：US11889403

申请日：2007-08-13

申请人： Koichi Nishikawa ,  Masaaki Shimizu ,  Kenichi Nonaka ,  Seiichi Yokoyama ,  Hideki Hashimoto

发明人： Koichi Nishikawa ,  Masaaki Shimizu ,  Kenichi Nonaka ,  Seiichi Yokoyama ,  Hideki Hashimoto

IPC分类号： H05K3/00 ,  H05B3/06

CPC分类号： H01L21/67115 ,  H01L21/67103 ,  H01L21/68721 ,  H01L29/1608 ,  H01L29/6606 ,  Y10T29/49117 ,  Y10T29/49124

摘要： A method of manufacturing a semiconductor device, includes increasing adherence between a susceptor as a heating element, and a semiconductor substrate disposed on the susceptor, by using an adherence increasing mechanism, or increasing heat transmitted to a semiconductor substrate, which is disposed on a susceptor as a heating element, by using a transmitted-heat increasing mechanism; and heating the semiconductor substrate to have a predetermined temperature by heating the susceptor. The adherence increasing mechanism may include the susceptor and one of a heavy-weight stone disposed on the semiconductor substrate, a cap disposed on the semiconductor substrate and engaged with the susceptor, and an adhesive layer provided between the susceptor and the semiconductor substrate. The transmitted-heat increasing mechanism may include the susceptor and small pieces which are disposed on the semiconductor substrate and have radiated-light absorption ability. The susceptor may hold a plurality of the semiconductor substrates in a stacked form.

摘要翻译： 一种制造半导体器件的方法包括通过使用附着增加机构增加作为加热元件的基座和设置在基座上的半导体基板之间的粘附性，或者增加传输到半导体基板的热量，该半导体基板设置在基座 作为加热元件，通过使用透热增加机构; 并且通过加热所述基座来加热所述半导体衬底以具有预定温度。 附着增加机构可以包括基座和设置在半导体衬底上的重量级的石块之一，设置在半导体衬底上并与基座接合的帽以及设置在基座和半导体衬底之间的粘合剂层。 透热增加机构可以包括设置在半导体衬底上并具有辐射光吸收能力的基座和小片。 基座可以以堆叠的形式保持多个半导体衬底。

公开(公告)号：US09273412B2

公开(公告)日：2016-03-01

申请号：US13527198

申请日：2012-06-19

申请人： Kunihiko Suzuki ,  Hideki Ito ,  Naohisa Ikeya ,  Hidekazu Tsuchida ,  Isaho Kamata ,  Masahiko Ito ,  Masami Naito ,  Hiroaki Fujibayashi ,  Ayumu Adachi ,  Koichi Nishikawa

发明人： Kunihiko Suzuki ,  Hideki Ito ,  Naohisa Ikeya ,  Hidekazu Tsuchida ,  Isaho Kamata ,  Masahiko Ito ,  Masami Naito ,  Hiroaki Fujibayashi ,  Ayumu Adachi ,  Koichi Nishikawa

IPC分类号： C30B25/10

摘要： A film-forming apparatus and method comprising a film-forming chamber for supplying a reaction gas into, a cylindrical shaped liner provided between an inner wall of the film-forming chamber and a space for performing a film-forming process, a main-heater for heating a substrate placed inside the liner, from the bottom side, a sub-heater cluster provided between the liner and the inner wall, for heating the substrate from the top side, wherein the main-heater and the sub-heater cluster are resistive heaters, wherein the sub-heater cluster has a first sub-heater provided at the closest position to the substrate, and a second sub-heater provided above the first sub-heater, wherein the first sub-heater heats the substrate in combination with the main-heater, the second sub-heater heats the liner at a lower output than the first sub-heater, wherein each temperature of the main-heater, the first sub-heater, and the second sub-heater is individually controlled.

公开(公告)号：US4719754A

公开(公告)日：1988-01-19

申请号：US802977

申请日：1985-11-29

申请人： Koichi Nishikawa

发明人： Koichi Nishikawa

IPC分类号： F03B13/24 ,  F03B13/14 ,  F03B13/12

CPC分类号： F03B13/142 ,  F05B2240/93 ,  Y02E10/32 ,  Y02E10/38

摘要： A wave-activated power generating apparatus in the form of a buoy includes a floatable main body provided with a vertically extending central pipe having its bottom open end opened into the water and its top open end located above the water surface when the main body floats in the water surface, an air turbine disposed at the top open end of the central pipe, a generator operatively coupled to the air turbine, and a plate-shaped guide plate fixedly attached to the main body as located opposite to and separated away from the bottom open end of the central pipe. The provision of the bottom guide plate allows to define a laterally opened circular opening between the guide plate and the bottom of the main body, through which the water moves into and out of the central pipe. This structure allows to use the present apparatus even in shallow waters. '

摘要翻译： 浮体形式的波浪式发电装置包括：浮动主体，其具有垂直延伸的中心管，当主体浮动时，其具有开口的水底部开口端和位于水面上方的顶部开口端 水表面，设置在中心管的顶部开口端的空气涡轮机，可操作地联接到空气涡轮机的发电机和固定地附接到主体的板状引导板，其位于与底部相对并分离的位置 中央管道的开口端。 底部引导板的设置允许在引导板和主体的底部之间限定横向打开的圆形开口，水通过其移动进入和离开中心管。 这种结构允许即使在浅水区域中使用本装置。