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公开(公告)号:US07544552B2
公开(公告)日:2009-06-09
申请号:US11386661
申请日:2006-03-23
申请人: Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
发明人: Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
IPC分类号: H01L21/337 , H01L29/772 , H01L21/339 , H01L21/338 , H01L29/768 , H01L29/78
CPC分类号: H01L29/7722
摘要: A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.
摘要翻译: 一种用于制造具有形成第一高电阻层的步骤的接合半导体器件的制造方法,形成沟道掺杂层的步骤,用于形成第二高电阻层的步骤,形成低电阻的步骤 作为源极区域的第一导电类型的层,用于对第二高电阻层和低电阻层的中间深度进行部分蚀刻的步骤,用于在第二高电阻层和低电阻层的蚀刻部分的下方形成栅极区域的步骤 蚀刻步骤,以及在栅极区域和源极区域之间的区域的表面上形成保护膜的步骤。 在表面中使用相对较低能量的离子注入,预先将蚀刻的源极区域的下表面和沟道掺杂层的上表面之间的高度形成为栅极区域。
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公开(公告)号:US20060216879A1
公开(公告)日:2006-09-28
申请号:US11386661
申请日:2006-03-23
申请人: Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
发明人: Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
IPC分类号: H01L21/337
CPC分类号: H01L29/7722
摘要: A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.
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公开(公告)号:US20060214268A1
公开(公告)日:2006-09-28
申请号:US11385762
申请日:2006-03-22
申请人: Yusuke Maeyama , Koichi Nishikawa , Yusuke Fukuda , Masaaki Shimizu , Masashi Satoh , Hiroaki Iwakuro , Kenichi Nonaka
发明人: Yusuke Maeyama , Koichi Nishikawa , Yusuke Fukuda , Masaaki Shimizu , Masashi Satoh , Hiroaki Iwakuro , Kenichi Nonaka
IPC分类号: H01L29/04
CPC分类号: H01L29/045 , H01L21/046 , H01L21/0485 , H01L29/6606 , H01L29/66068
摘要: A semiconductor device includes: a passivation film; a first semiconductor layer that has a first main component of 4H—SiC of a first conductivity type; and a second semiconductor layer that has a second main component of 4H—SiC of a second conductivity type. The second semiconductor layer has a pn-junction with the first semiconductor layer. The pn-junction has a junction edge. The first and second semiconductor layers further include a local area that includes the junction edge. The local area has a first principal plane that interfaces with the passivation film. A normal to the first principal plane tilts by a first tilt angle in a range of 25 degrees to 45 degrees from a first axis of [0001] or [000-1] toward a second axis of .
摘要翻译: 一种半导体器件包括:钝化膜; 具有第一导电类型的4H-SiC的第一主要成分的第一半导体层; 以及具有第二导电类型的4H-SiC的第二主要成分的第二半导体层。 第二半导体层具有与第一半导体层的pn结。 pn结具有接合边缘。 第一和第二半导体层还包括包括接合边缘的局部区域。 局部区域具有与钝化膜相接的第一主平面。 第一主平面的法线在从[0001]或[000-1]的第一轴朝向<01-10>的第二轴的25度至45度的范围内倾斜第一倾斜角。
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公开(公告)号:US20110169015A1
公开(公告)日:2011-07-14
申请号:US13060697
申请日:2009-08-25
申请人: Yuki Negoro , Akihiko Horiuchi , Kensuke Iwanaga , Seiichi Yokoyama , Hideki Hashimoto , Kenichi Nonaka , Yusuke Maeyama , Masashi Sato , Masaaki Shimizu
发明人: Yuki Negoro , Akihiko Horiuchi , Kensuke Iwanaga , Seiichi Yokoyama , Hideki Hashimoto , Kenichi Nonaka , Yusuke Maeyama , Masashi Sato , Masaaki Shimizu
IPC分类号: H01L29/161 , H01L21/56
CPC分类号: H01L29/732 , H01L23/3171 , H01L23/3192 , H01L29/045 , H01L29/1608 , H01L29/42304 , H01L29/6606 , H01L29/66068 , H01L29/6609 , H01L29/66295 , H01L29/66416 , H01L29/7722 , H01L29/8613 , H01L2224/06181 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
摘要: Disclosed is a bipolar semiconductor device which is capable of reducing the surface state density of a bipolar transistor and increasing the current gain of the transistor, thereby improving the transistor performance. A bipolar semiconductor device (100) has a surface protective film (30) on the surface of a semiconductor element. The surface protective film is composed of a thermal oxide film (31) formed on the surface of the semiconductor element, and a deposited oxide film (32) formed on the thermal oxide film. The deposited oxide film contains at least one of hydrogen element and nitrogen element in an amount of not less than 1018 cm−3.
摘要翻译: 公开了能够降低双极晶体管的表面状态密度并增加晶体管的电流增益的双极半导体器件,从而提高晶体管的性能。 双极半导体器件(100)在半导体元件的表面上具有表面保护膜(30)。 表面保护膜由形成在半导体元件的表面上的热氧化膜(31)和形成在热氧化膜上的沉积氧化物膜(32)构成。 沉积的氧化物膜含有不少于1018cm-3的氢元素和氮元素中的至少一种。
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公开(公告)号:US08937319B2
公开(公告)日:2015-01-20
申请号:US13410542
申请日:2012-03-02
IPC分类号: H01L29/872 , H01L29/06 , H01L29/16
CPC分类号: H01L29/872 , H01L29/0619 , H01L29/0649 , H01L29/1608
摘要: A third insulating layer is formed in a periphery region of a substrate over a first surface (main surface) of the substrate so as to straddle a second semiconductor layer closest to a guard ring layer and a second semiconductor layer closest to the second semiconductor layer. In other words, the third insulating layer is formed to cover a portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers. Thereby, the third insulating layer electrically insulates the metal layer from the portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers.
摘要翻译: 在基板的第一表面(主表面)上的基板的周边区域中形成第三绝缘层,以跨越最靠近保护环层的第二半导体层和最靠近第二半导体层的第二半导体层。 换句话说,第三绝缘层被形成为覆盖暴露于基板的第一表面(主表面)并且位于第二半导体层之间的第一半导体层的一部分。 由此,第三绝缘层将金属层与暴露于基板的第一表面(主表面)并且位于第二半导体层之间的第一半导体层的部分电绝缘。
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