公开(公告)号：US6150690A

公开(公告)日：2000-11-21

申请号：US30072

申请日：1998-02-25

申请人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Toru Ozaki

发明人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Toru Ozaki

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10885 ,  H01L28/91 ,  H01L27/10852 ,  H01L27/10873

摘要： Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.

公开(公告)号：US06303429B1

公开(公告)日：2001-10-16

申请号：US09676084

申请日：2000-10-02

申请人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

发明人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

IPC分类号： H01L218242

CPC分类号： H01L27/10885 ,  H01L27/10852 ,  H01L27/10873 ,  H01L28/91

摘要： Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.

摘要翻译： 电容器形成在由氧化硅制成的层间绝缘体中制成的沟槽中。 绝缘膜（例如，氮化硅膜）设置在层间绝缘体的每个沟槽的侧面上。 在层间绝缘体的每个沟槽中设置由钌等制成的存储电极。 在存储电极上形成由BSTO等构成的电容绝缘膜。 在电容器绝缘膜上形成由钌等制成的平板电极。 平板电极对所有提供的电容器是共同的。 任何两个相邻的电容器通过层间绝缘体和设置在层间绝缘体的沟槽的侧面上的绝缘膜电隔离。

公开(公告)号：US06635933B2

公开(公告)日：2003-10-21

申请号：US09953306

申请日：2001-09-17

申请人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

发明人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

IPC分类号： H01L2976

CPC分类号： H01L27/10885 ,  H01L27/10852 ,  H01L27/10873 ,  H01L28/91

摘要： Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.

公开(公告)号：US08740470B2

公开(公告)日：2014-06-03

申请号：US13392975

申请日：2011-09-13

申请人： Yutaka Ishibashi ,  Makoto Watanabe ,  Tetsuya Takahashi

发明人： Yutaka Ishibashi ,  Makoto Watanabe ,  Tetsuya Takahashi

IPC分类号： F16C33/48

CPC分类号： F16C33/467 ,  F16C33/4635 ,  F16C33/4676 ,  F16C33/4694 ,  F16C33/516 ,  F16C33/66 ,  F16C33/6681

摘要： A pair of rim portions (4a) and (4b) is formed in the shape of a discontinuous segmental circular ring, which includes cutout portions (8a) and (8b), respectively, at one position. The cutout portions of the respective rim portions are concentrically disposed so as to face each other with a predetermined interval therebetween in an axial direction while having the same phase in a circumferential direction. A plurality of pillar portions (6) form pockets (10) where rollers (14) are retained. An expandable elastic connecting portion (12), which connects one end portion (84a) of one rim portion in the circumferential direction to the other end portion (82b) of the other rim portion in the circumferential direction, is provided at the pair of rim portions.

摘要翻译： 一对边缘部分（4a）和（4b）分别形成在一个位置处包括切口部分（8a）和（8b）的不连续分段圆环形状。 各个边缘部分的切口部分在轴向方向上以预定的间隔彼此相对地同心地设置，同时在圆周方向上具有相同的相位。 多个柱部（6）形成保持辊（14）的凹部（10）。 在圆周方向上将一个边缘部分的一个端部（84a）沿着圆周方向连接到另一个边缘部分的另一端部（82b）的可膨胀弹性连接部分（12）设置在所述一对边缘 部分。

公开(公告)号：US06336296B1

公开(公告)日：2002-01-08

申请号：US09472810

申请日：1999-12-28

申请人： Yutaka Ishibashi ,  Shigeru Fujimoto ,  Isako Tsushima ,  Yoshio Kojima ,  Junko Oikawa

发明人： Yutaka Ishibashi ,  Shigeru Fujimoto ,  Isako Tsushima ,  Yoshio Kojima ,  Junko Oikawa

IPC分类号： E04C252

CPC分类号： E04F15/02476 ,  E04F15/02405 ,  E04F15/02411

摘要： A floor system includes a plurality of panels placed on a base floor. A space is formed between the panels and the base floor for laying cables. A plurality of sliding plates are arranged on the base floor. A plurality of supports are provided and each support of the plurality of supports is arranged on each of the sliding plates so as to freely slide. The plurality of panels are supported by the plurality of supports by being fixed on a pedestal of the each support of the plurality of supports. The plurality of panels are hence connected to each other to form a single floor surface. The dynamic coefficient of friction between the bottom of the supports and the sliding plates is selected to be a value within a range of 0.09 to 0.25.

摘要翻译： 地板系统包括放置在底座上的多个面板。 在面板和基座之间形成用于铺设电缆的空间。 多个滑板布置在底座上。 提供多个支撑件，并且每个支撑件的每个支撑件布置在每个滑板上以便自由滑动。 多个面板通过固定在多个支撑件的每个支撑件的基座上由多个支撑件支撑。 因此，多个面板彼此连接以形成单个地板表面。 支撑体底部和滑板之间的动态摩擦系数选择为0.09〜0.25的范围内的值。

公开(公告)号：US5672891A

公开(公告)日：1997-09-30

申请号：US638216

申请日：1996-04-26

申请人： Takeshi Hamamoto ,  Takashi Yamada ,  Yutaka Ishibashi

发明人： Takeshi Hamamoto ,  Takashi Yamada ,  Yutaka Ishibashi

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/108 ,  H01L27/10829

摘要： A semiconductor memory device comprises a semiconductor substrate having memory cell area, a plurality of trenches selectively formed in the memory cell area aligning in certain intervals and a plurality of memory cell arrays provided in the memory cell area, wherein each of the memory cell arrays comprises a plurality of MOS transistors connected in a serial array and a plurality of capacitors each formed in a corresponding one of the trenches. Each of the transistors has a gate electrode above the substrate with a gate insulating film formed therebetween and source and drain regions formed in the substrate on both sides of the gate electrode. Each of the capacitors includes a charge storage layer formed on an inner wall of each of the trenches and connected integrally to one of the source and drain regions of each of the transistors, a capacitor insulating film formed on the charge storage layer and a capacitor electrode formed on the capacitor insulating film so as to bury each of the trenches and extending to the surface of the substrate, which is formed on the surface of the substrate except for at least formation areas of the transistors.

摘要翻译： 一种半导体存储器件包括具有存储单元区域的半导体衬底，选择性地形成在存储单元区域中以一定间隔对准的多个沟槽和设置在存储单元区域中的多个存储单元阵列，其中每个存储单元阵列包括 以串联阵列连接的多个MOS晶体管和分别形成在对应的一个沟槽中的多个电容器。 每个晶体管在衬底之上具有栅极电极，栅极绝缘膜形成在其间，源极和漏极区域形成在栅电极两侧的衬底中。 每个电容器包括形成在每个沟槽的内壁上并且与每个晶体管的源极和漏极区中的一个一体连接的电荷存储层，形成在电荷存储层上的电容器绝缘膜和电容器电极 形成在电容器绝缘膜上，以埋入每个沟槽并且延伸到形成在基板的表面上的基板的表面，除了晶体管的至少形成区域之外。

公开(公告)号：USD379945S

公开(公告)日：1997-06-17

申请号：US46827

申请日：1995-11-16

申请人： Hiroyuki Kawase ,  Yutaka Ishibashi

设计人： Hiroyuki Kawase ,  Yutaka Ishibashi

公开(公告)号：US09004775B2

公开(公告)日：2015-04-14

申请号：US13392761

申请日：2011-09-13

申请人： Yutaka Ishibashi

发明人： Yutaka Ishibashi

IPC分类号： F16C33/46

CPC分类号： F16C33/4694 ,  F16C19/463 ,  F16C33/4635 ,  F16C2226/70

摘要： The present invention provides a single-split cage capable of continuously holding a plurality of rolling elements stably for a long time by eliminating the difference in the strength between split regions, by maintaining the strength of the entire cage uniform in the circumferential direction and by maintaining the dimensional accuracy between the split regions constant at the time of molding and also capable of improving load capacity and achieving low cost for assembly. A split section 10 for splitting at one portion in the circumferential direction is formed at regions (split regions 10a and 10b) extending between pockets 2p adjacent to each other in the circumferential direction, engagement sections being engageable with each other are provided at the circumferential central position between the pockets and on a one-side split face Sa and the other-side split face Sb formed by splitting the regions, and in a state in which both the engagement sections are engaged with each other, predetermined clearances are formed between the one-side split face and the other-side split face and between the engagement sections.

摘要翻译： 本发明提供一种能够通过将保持整个保持架的强度在圆周方向上均匀并且通过维持在一起的长度保持多个滚动元件而能够通过消除分割区域之间的强度的差异而连续保持多个滚动元件的单分离式保持架 分割区域之间的尺寸精度在成型时恒定，并且还能够提高负载能力并且实现低的组装成本。 在圆周方向上彼此相邻的凹穴2p之间延伸的区域（分割区域10a和10b）处形成有用于在圆周方向上的一个部分处分开的分割部分10，在周向中心 在一个侧面分开面Sa和另一侧分割面Sb之间形成凹槽之间的位置，并且在两个接合部彼此接合的状态下，在一个侧面之间形成预定的间隙 并且在接合部之间。

公开(公告)号：US20120275741A1

公开(公告)日：2012-11-01

申请号：US13392761

申请日：2011-09-13

申请人： Yutaka Ishibashi

发明人： Yutaka Ishibashi

IPC分类号： F16C33/46

CPC分类号： F16C33/4694 ,  F16C19/463 ,  F16C33/4635 ,  F16C2226/70

摘要： The present invention provides a single-split cage capable of continuously holding a plurality of rolling elements stably for a long time by eliminating the difference in the strength between split regions, by maintaining the strength of the entire cage uniform in the circumferential direction and by maintaining the dimensional accuracy between the split regions constant at the time of molding and also capable of improving load capacity and achieving low cost for assembly. A split section 10 for splitting at one portion in the circumferential direction is formed at regions (split regions 10a and 10b) extending between pockets 2p adjacent to each other in the circumferential direction, engagement sections being engageable with each other are provided at the circumferential central position between the pockets and on a one-side split face Sa and the other-side split face Sb formed by splitting the regions, and in a state in which both the engagement sections are engaged with each other, predetermined clearances are formed between the one-side split face and the other-side split face and between the engagement sections.

摘要翻译： 本发明提供一种能够通过将保持整个保持架的强度在圆周方向上均匀并且通过维持在一起的长度保持多个滚动元件而能够通过消除分割区域之间的强度的差异而连续保持多个滚动元件的单分离式保持架 分割区域之间的尺寸精度在成型时恒定，并且还能够提高负载能力并且实现低的组装成本。 在圆周方向上彼此相邻的凹穴2p之间延伸的区域（分割区域10a和10b）处形成有用于在圆周方向上的一个部分处分开的分割部分10，在周向中心 在一个侧面分开面Sa和另一侧分割面Sb之间形成凹槽之间的位置，并且在两个接合部彼此接合的状态下，在一个侧面之间形成预定的间隙 并且在接合部之间。

公开(公告)号：US08274809B2

公开(公告)日：2012-09-25

申请号：US12855151

申请日：2010-08-12

申请人： Takeshi Murata ,  Yutaka Ishibashi ,  Hiroyuki Nitta

发明人： Takeshi Murata ,  Yutaka Ishibashi ,  Hiroyuki Nitta

IPC分类号： G11C5/02

CPC分类号： G11C5/063 ,  G11C11/22 ,  G11C13/0007 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021

摘要： According to one embodiment, a semiconductor storage device includes a plurality of parallel first interconnects extending in a first direction, a plurality of parallel second interconnects which extend in a second direction perpendicular to the first direction and which make a two-level crossing with respect to the first interconnects, and memory cell structures provided in regions where the first interconnects and the second interconnects make two-level crossings, the memory cell structures being connected on one end to the first interconnects and connected on the other end to the second interconnects, the memory cell structure including a variable resistive element and a non-ohmic element which are connected in series, wherein the endmost first interconnect is disconnected in at least one portion.

摘要翻译： 根据一个实施例，半导体存储装置包括在第一方向上延伸的多个平行的第一互连件，多个平行的第二互连件，其沿与第一方向垂直的第二方向延伸，并且相对于 所述第一互连和存储单元结构设置在所述第一互连和所述第二互连构成两级交叉的区域中，所述存储单元结构的一端连接到所述第一互连并在另一端连接到所述第二互连， 存储单元结构包括串联连接的可变电阻元件和非欧姆元件，其中最末端的第一互连件在至少一部分中断开。