公开(公告)号：US06544904B1

公开(公告)日：2003-04-08

申请号：US10157882

申请日：2002-05-31

申请人： Yuuki Kamiura ,  Hiroshi Tobimatsu ,  Kouji Oda ,  Mahito Sawada ,  Koji Shibata ,  Hiroyuki Kawata

发明人： Yuuki Kamiura ,  Hiroshi Tobimatsu ,  Kouji Oda ,  Mahito Sawada ,  Koji Shibata ,  Hiroyuki Kawata

IPC分类号： H01L2131

CPC分类号： H01L21/76802 ,  H01L21/31144 ,  H01L21/76832 ,  H01L24/05 ,  H01L2924/351 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device is provided, which prevents a polyimide film from coming unstuck from a film to be subjected to isotropic etching, and further prevents deposits adhered to respective side faces of the films from coming off, during a heat treatment for imidizing the polyimide film. Isotropic etching is performed on a silicon nitride film 4 using, as a mask, a polyimide film 5 having a predetermined pattern formed therein. Next, a heat treatment is carried out to imidize the polyimide film 5 prior to performing anisotropic etching on a silicon oxide film 3. During the heat treatment for imidizing the polyimide film 5, since deposits, which are to be generated by anisotropic etching, are not yet adhered to the respective side faces of the films, the polyimide film 5 does not come unstuck from the silicon nitride film 4. Further, the deposits which are adhered to the respective side face of the films after the heat treatment will not come off.

摘要翻译： 提供一种制造半导体器件的方法，其防止聚酰亚胺膜从薄膜脱落以进行各向同性蚀刻，并且进一步防止在用于酰亚胺化的热处理期间粘附到膜的各个侧面的沉积物脱落 聚酰亚胺薄膜。 在氮化硅膜4上进行各向同性蚀刻，使用形成有预定图案的聚酰亚胺膜5作为掩模。 接下来，在对氧化硅膜3进行各向异性蚀刻之前，进行热处理以对聚酰亚胺膜5进行酰亚胺化。在酰亚胺化聚酰亚胺膜5的热处理中，由于通过各向异性蚀刻产生的沉积物为 还没有粘附到膜的各个侧面，聚酰亚胺膜5不会从氮化硅膜4脱落。此外，附着在热处理后的膜的相应侧面的沉积物将不会脱落 。

公开(公告)号：US06645859B1

公开(公告)日：2003-11-11

申请号：US10170579

申请日：2002-06-14

申请人： Mahito Sawada ,  Hiroshi Tobimatsu ,  Kouji Oda ,  Yuuki Kamiura ,  Kouji Shibata ,  Hiroyuki Kawata

发明人： Mahito Sawada ,  Hiroshi Tobimatsu ,  Kouji Oda ,  Yuuki Kamiura ,  Kouji Shibata ,  Hiroyuki Kawata

IPC分类号： H01L2144

CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837

摘要： A manufacturing method of a semiconductor device allowing successful filling of an insulating film by HDP-CVD (High Density Plasma-Chemical Vapor Deposition) in a gap or valley between densely placed interconnections is provided. The method includes the steps of forming semiconductor elements on a semiconductor substrate, forming on the semiconductor elements a plurality of interconnections with top protective layers side by side to electrically connect the semiconductor elements, forming a protective insulating film by CVD other than HDP-CVD to cover top and side surfaces of the interconnections and a bottom surface of a gap between the interconnections, and forming an insulating film by HDP-CVD to cover the protective insulating film and to fill in the gap between the interconnections covered with the protective insulating film.

摘要翻译： 提供了通过HDP-CVD（高密度等离子体 - 化学气相沉积）在密集布置的互连之间的间隙或谷中成功地填充绝缘膜的半导体器件的制造方法。 该方法包括以下步骤：在半导体衬底上形成半导体元件，在半导体元件上形成与顶部保护层并排的多个互连以电连接半导体元件，通过除HDP-CVD之外的CVD形成保护绝缘膜以形成保护绝缘膜 互连的顶盖和侧表面以及互连之间的间隙的底表面，并且通过HDP-CVD形成绝缘膜以覆盖保护绝缘膜并填充被保护绝缘膜覆盖的互连之间的间隙。

公开(公告)号：US06759317B2

公开(公告)日：2004-07-06

申请号：US09910824

申请日：2001-07-24

申请人： Hiroshi Tobimatsu ,  Yuuki Kamiura ,  Seiji Okura ,  Mahito Sawada

发明人： Hiroshi Tobimatsu ,  Yuuki Kamiura ,  Seiji Okura ,  Mahito Sawada

IPC分类号： H01L2144

CPC分类号： H01L21/76804

摘要： An interconnection is formed on a semiconductor substrate having a semiconductor element formed thereon. Next, a passivation film is formed on the semiconductor substrate including the interconnection. Further, a polyimide film, which is served as a buffer coating film, is formed on the passivation film. Further, the polyimide film is patterned. Next, the passivation film is subject to etching while the patterned polyimide film is taken as a mask. Next, a hardened layer, which is formed on the surface of the polyimide film as a result of etching, is removed through ashing process. Next, the semiconductor substrate after ashing process is cured so as to transform the polyimide film into imide.

摘要翻译： 在其上形成有半导体元件的半导体衬底上形成互连。 接下来，在包括互连的半导体衬底上形成钝化膜。 此外，在钝化膜上形成用作缓冲涂膜的聚酰亚胺膜。 此外，对聚酰亚胺膜进行图案化。 接下来，在将图案化的聚酰亚胺膜作为掩模的同时，钝化膜进行蚀刻。 接下来，通过灰化处理去除在聚酰亚胺膜的表面上形成的蚀刻结果的硬化层。 接下来，使灰化处理后的半导体基板固化，将聚酰亚胺膜变为酰亚胺。

公开(公告)号：US20070096322A1

公开(公告)日：2007-05-03

申请号：US11635495

申请日：2006-12-08

申请人： Koyu Asai ,  Hiroshi Tobimatsu ,  Hiroyuki Kawata ,  Mahito Sawada

发明人： Koyu Asai ,  Hiroshi Tobimatsu ,  Hiroyuki Kawata ,  Mahito Sawada

IPC分类号： H01L23/52

CPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.

摘要翻译： 互连设置有连接到互连体的虚拟互连，并且虚设互连设置有应力集中部，其中产生比互连体高的拉伸应力。 在应力集中部分附近，设置通过高密度等离子体CVD形成的绝缘膜，并且通过绝缘膜在应力集中部分产生拉伸应力。 利用这种结构，可以防止在互连体中的任何位置发生空隙。

公开(公告)号：US07489040B2

公开(公告)日：2009-02-10

申请号：US11635495

申请日：2006-12-08

申请人： Koyu Asai ,  Hiroshi Tobimatsu ,  Hiroyuki Kawata ,  Mahito Sawada

发明人： Koyu Asai ,  Hiroshi Tobimatsu ,  Hiroyuki Kawata ,  Mahito Sawada

IPC分类号： H01L23/48

CPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.

摘要翻译： 互连设置有连接到互连体的虚拟互连，并且虚设互连设置有应力集中部，其中产生比互连体高的拉伸应力。 在应力集中部分附近，设置通过高密度等离子体CVD形成的绝缘膜，并且通过绝缘膜在应力集中部分产生拉伸应力。 利用这种结构，可以防止在互连体中的任何位置发生空隙。

公开(公告)号：US07154184B2

公开(公告)日：2006-12-26

申请号：US10725384

申请日：2003-12-03

申请人： Koyu Asai ,  Hiroshi Tobimatsu ,  Hiroyuki Kawata ,  Mahito Sawada

发明人： Koyu Asai ,  Hiroshi Tobimatsu ,  Hiroyuki Kawata ,  Mahito Sawada

IPC分类号： H01L23/48

CPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.

公开(公告)号：US6046488A

公开(公告)日：2000-04-04

申请号：US985218

申请日：1997-12-04

申请人： Takahiro Kawasaki ,  Shigeru Harada ,  Hiroshi Tobimatsu

发明人： Takahiro Kawasaki ,  Shigeru Harada ,  Hiroshi Tobimatsu

IPC分类号： H01L21/82 ,  H01L21/311 ,  H01L21/768 ,  H01L23/525 ,  H01L23/58 ,  H01L29/00

CPC分类号： H01L21/76801 ,  H01L21/31144 ,  H01L23/5258 ,  H01L23/585 ,  H01L2924/0002

摘要： A semiconductor device allowing the manufacturing process to be simplified and fine structures therein to be readily formed and a manufacturing method thereof are provided. In the semiconductor device, a conductive layer is used as a mask during etching for forming a first opening.

摘要翻译： 能够容易地形成容易形成制造工序的半导体装置及其精细结构及其制造方法。 在半导体器件中，在用于形成第一开口的蚀刻期间，使用导电层作为掩模。

公开(公告)号：US20060022321A1

公开(公告)日：2006-02-02

申请号：US11190011

申请日：2005-07-27

申请人： Kazuhito Matsukawa ,  Tsuyoshi Koga ,  Akio Nishida ,  Yoshiko Higashide ,  Jun Shibata ,  Hiroshi Tobimatsu

发明人： Kazuhito Matsukawa ,  Tsuyoshi Koga ,  Akio Nishida ,  Yoshiko Higashide ,  Jun Shibata ,  Hiroshi Tobimatsu

IPC分类号： H01L21/50 ,  H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 μm or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

公开(公告)号：US5126828A

公开(公告)日：1992-06-30

申请号：US501211

申请日：1990-03-29

申请人： Muneo Hatta ,  Susumu Takeuchi ,  Hiroshi Tobimatsu

发明人： Muneo Hatta ,  Susumu Takeuchi ,  Hiroshi Tobimatsu

IPC分类号： H01L21/822 ,  H01L21/60 ,  H01L21/66 ,  H01L23/485 ,  H01L23/50 ,  H01L23/58 ,  H01L27/04 ,  H01L29/06

CPC分类号： H01L29/0657 ,  H01L22/32 ,  H01L24/05 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15312

摘要： A WSI device comprises a semiconductor substrate having a wafer scale size. An integrated circuit having a unified function is formed on a main surface of the semiconductor substrate. The semiconductor substrate defines various cutouts centrally and/or peripherally thereof. The cutouts serve to extend peripheral regions of the semiconductor substrate. Bonding pads are formed along the extended peripheral regions of the semiconductor substrate. As a result, the number of bonding pads that can be formed is increased to promote multi-functioning of the WSI device.

摘要翻译： WSI器件包括具有晶片刻度尺寸的半导体衬底。 具有统一功能的集成电路形成在半导体衬底的主表面上。 半导体衬底在其中心和/或周边限定各种切口。 切口用于延伸半导体衬底的周边区域。 沿着半导体衬底的延伸的周边区域形成接合焊盘。 结果，可以形成的接合焊盘的数量增加，以促进WSI器件的多功能化。

公开(公告)号：US20110070731A1

公开(公告)日：2011-03-24

申请号：US12955661

申请日：2010-11-29

申请人： Takuya FUTASE ,  Hiroshi Tobimatsu

发明人： Takuya FUTASE ,  Hiroshi Tobimatsu

IPC分类号： H01L21/768

CPC分类号： H01L21/28518 ,  H01L21/02063 ,  H01L21/2855 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/6831 ,  H01L21/76814 ,  H01L21/76846

摘要： To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment is performed to a principal surface of the semiconductor wafer by supplying reducing gas, sequentially, heat treatment is performed to the semiconductor wafer at a first temperature of 100 to 150° C. by a showerhead which is maintained at 180° C. Next, after the semiconductor wafer is vacuum transferred from the chamber to a chamber for heat treatment, heat treatment is performed to the semiconductor wafer at a second temperature of 150 to 400° C. in the chamber, thereby removing a product remaining over the principal surface of the semiconductor wafer.

摘要翻译： 提供能够通过减少连接孔部分的电气特性的变化来提高半导体器件的可靠性和制造成品率的技术。 在将半导体晶片放置在设置在用于沉积系统的干洗处理的室中的晶片台上之后，通过供应还原气体对半导体晶片的主表面进行干洗处理，依次对半导体进行热处理 晶片在100〜150℃的第一温度下通过保持在180℃的喷头。接下来，在将半导体晶片从腔室真空转移到用于热处理的室之后，对半导体晶片进行热处理 在腔室中的第二温度为150至400℃，从而除去残留在半导体晶片的主表面上的产物。