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公开(公告)号:US08384196B2
公开(公告)日:2013-02-26
申请号:US13243521
申请日:2011-09-23
申请人: Zhiyuan Cheng , James Fiorenza , Jennifer M. Hydrick , Anthony J. Lochtefeld , Ji-Soo Park , Jie Bai , Jizhong Li
发明人: Zhiyuan Cheng , James Fiorenza , Jennifer M. Hydrick , Anthony J. Lochtefeld , Ji-Soo Park , Jie Bai , Jizhong Li
IPC分类号: H01L29/06
CPC分类号: H01L21/02538 , H01L21/02381 , H01L21/0245 , H01L21/02461 , H01L21/02463 , H01L21/02543 , H01L21/02546 , H01L21/02636 , H01L21/02639 , H01L21/02647 , H01L29/205 , H01L31/0687 , H01L31/06875 , H01L31/1808 , H01L31/1852 , H01L31/1892 , Y02E10/544
摘要: Methods and structures are provided for formation of devices on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer.
摘要翻译: 提供了通过使用纵横比捕获和外延层过度生长来形成衬底上的器件的方法和结构,包括例如晶格失配的材料。 一种方法包括在设置在包括第一半导体材料的基板上的掩模层中形成开口。 在开口内形成包括与第一半导体材料晶格失配的第二半导体材料的第一层。 第一层具有足以在掩模层的顶表面上方延伸的厚度。 包括第二半导体材料的第二层形成在第一层上并且在掩模层的至少一部分之上。 第一层的垂直生长速率大于第一层的横向生长速率,第二层的横向生长速率大于第二层的垂直生长速率。
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公开(公告)号:US08981427B2
公开(公告)日:2015-03-17
申请号:US12503597
申请日:2009-07-15
IPC分类号: H01L21/02 , H01L21/306 , H01L21/28
CPC分类号: H01L21/30625 , H01L21/02057 , H01L21/02063 , H01L21/02065 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02488 , H01L21/02494 , H01L21/02532 , H01L21/02538 , H01L21/0262 , H01L21/02639 , H01L21/28255 , H01L21/28264 , H01L21/30604 , H01L21/31053 , H01L21/31055
摘要: A device includes a crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by using a planarization process configured with a selectivity of the crystalline material to the insulator greater than one. In a preferred embodiment, the planarization process uses a composition including abrasive spherical silica, H2O2 and water. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.
摘要翻译: 一种器件包括在由绝缘体限制的区域内的结晶材料。 结晶材料的表面具有减小的粗糙度。 一个实例包括通过使用配置有大于1的结晶材料对绝缘体的选择性的平坦化工艺来获得具有减小的粗糙度的表面。 在优选的实施方案中,平坦化方法使用包括研磨球形二氧化硅,H 2 O 2和水的组合物。 在优选实施例中,由绝缘体限制的区域是具有足以使用ART技术捕获缺陷的纵横比的绝缘体中的开口。
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公开(公告)号:US20100012976A1
公开(公告)日:2010-01-21
申请号:US12503597
申请日:2009-07-15
IPC分类号: H01L29/267 , H01L21/20 , H01L29/04
CPC分类号: H01L21/30625 , H01L21/02057 , H01L21/02063 , H01L21/02065 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02488 , H01L21/02494 , H01L21/02532 , H01L21/02538 , H01L21/0262 , H01L21/02639 , H01L21/28255 , H01L21/28264 , H01L21/30604 , H01L21/31053 , H01L21/31055
摘要: A device includes a crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by using a planarization process configured with a selectivity of the crystalline material to the insulator greater than one. In a preferred embodiment, the planarization process uses a composition including abrasive spherical silica, H2O2 and water. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.
摘要翻译: 一种器件包括在由绝缘体限制的区域内的结晶材料。 结晶材料的表面具有减小的粗糙度。 一个实例包括通过使用配置有大于1的结晶材料对绝缘体的选择性的平坦化工艺来获得具有减小的粗糙度的表面。 在优选的实施方案中,平坦化方法使用包括研磨球形二氧化硅,H 2 O 2和水的组合物。 在优选实施例中,由绝缘体限制的区域是具有足以使用ART技术捕获缺陷的纵横比的绝缘体中的开口。
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