公开(公告)号：US08877599B2

公开(公告)日：2014-11-04

申请号：US13471986

申请日：2012-05-15

申请人： Ziwei Fang ,  Tsan-Chun Wang ,  De-Wei Yu

发明人： Ziwei Fang ,  Tsan-Chun Wang ,  De-Wei Yu

IPC分类号： H01L21/33

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7847

摘要： A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.

摘要翻译： 公开了一种具有位错的半导体器件和制造半导体器件的方法。 用于制造半导体器件的示例性半导体器件和方法增强载流子迁移率。 该方法包括提供其中具有隔离特性的衬底和覆盖衬底的两个栅极叠层，其中一个栅极堆叠位于隔离特征顶部。 该方法还包括在衬底上执行预非晶体注入工艺。 该方法还包括在衬底上形成应力膜。 该方法还包括对衬底和应力膜进行退火处理。

公开(公告)号：US20130309829A1

公开(公告)日：2013-11-21

申请号：US13471986

申请日：2012-05-15

申请人： Ziwei Fang ,  Tsan-Chun Wang ,  De-Wei Yu

发明人： Ziwei Fang ,  Tsan-Chun Wang ,  De-Wei Yu

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7847

摘要： A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.

摘要翻译： 公开了一种具有位错的半导体器件和制造半导体器件的方法。 用于制造半导体器件的示例性半导体器件和方法增强载流子迁移率。 该方法包括提供其中具有隔离特性的衬底和覆盖衬底的两个栅极叠层，其中一个栅极堆叠位于隔离特征顶部。 该方法还包括在衬底上执行预非晶体注入工艺。 该方法还包括在衬底上形成应力膜。 该方法还包括对衬底和应力膜进行退火处理。

公开(公告)号：US09881840B2

公开(公告)日：2018-01-30

申请号：US13157179

申请日：2011-06-09

申请人： Yu-Lien Huang ,  Ziwei Fang ,  Tsan-Chun Wang ,  Chii-Ming Wu ,  Chun Hsiung Tsai

发明人： Yu-Lien Huang ,  Ziwei Fang ,  Tsan-Chun Wang ,  Chii-Ming Wu ,  Chun Hsiung Tsai

IPC分类号： H01L21/8238 ,  H01L21/3115 ,  H01L21/033 ,  H01L21/3213

CPC分类号： H01L21/823814 ,  H01L21/0337 ,  H01L21/31155 ,  H01L21/32139 ,  H01L21/823807

摘要： A hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided on the hard mask layer to transform the hard mask layer to be more resistant to wet etching solution. A patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.

公开(公告)号：US08999794B2

公开(公告)日：2015-04-07

申请号：US13183043

申请日：2011-07-14

申请人： Ziwei Fang ,  Ying Zhang ,  Jeff J. Xu

发明人： Ziwei Fang ,  Ying Zhang ,  Jeff J. Xu

IPC分类号： H01L21/336 ,  H01L21/306 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/3065

CPC分类号： H01L21/30617 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 在一个示例中，该方法包括在衬底上形成栅极结构; 在衬底中形成掺杂区域; 执行第一蚀刻工艺以去除掺杂区域并在衬底中形成沟槽; 以及执行通过去除衬底的部分来修改沟槽的第二蚀刻工艺。

公开(公告)号：US08877602B2

公开(公告)日：2014-11-04

申请号：US13156939

申请日：2011-06-09

申请人： Yu-Lien Huang ,  Chun Hsiung Tsai ,  Chii-Ming Wu ,  Ziwei Fang

发明人： Yu-Lien Huang ,  Chun Hsiung Tsai ,  Chii-Ming Wu ,  Ziwei Fang

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76229

摘要： The embodiments described provide mechanisms for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD0 gapfill for advanced processing technology.

摘要翻译： 所描述的实施例提供了用碳掺杂STI中的氧化物的机制，以使窄和宽结构中的蚀刻速率相等并且也使得宽STI的拐角变强。 这种碳掺杂可以通过离子束（离子注入）或通过等离子体掺杂来进行。 硬掩模层可用于保护下面的硅不被掺杂。 通过使用掺杂机制，硅和STI的均匀表面形貌使得门结构和ILD0间隙填充的图案化能够用于先进的加工技术。

公开(公告)号：US20090061605A1

公开(公告)日：2009-03-05

申请号：US12267193

申请日：2008-11-07

申请人： Ludovic GODET ,  George D. Papasouliotis ,  Ziwei Fang ,  Richard Appel ,  Vincent Deno ,  Vikram Singh ,  Harold M. Persing

发明人： Ludovic GODET ,  George D. Papasouliotis ,  Ziwei Fang ,  Richard Appel ,  Vincent Deno ,  Vikram Singh ,  Harold M. Persing

IPC分类号： H01L21/265

CPC分类号： H01J37/3171 ,  H01J37/32412 ,  H01J37/32935 ,  H01J2237/31705 ,  H01L21/2236

摘要： A method to provide a dopant profile adjustment solution in plasma doping systems for meeting both concentration and junction depth requirements. Bias ramping and bias ramp rate adjusting may be performed to achieve a desired dopant profile so that surface peak dopant profiles and retrograde dopant profiles are realized. The method may include an amorphization step in one embodiment.

摘要翻译： 在等离子体掺杂系统中提供掺杂剂分布调整溶液以满足浓度和结深度要求的方法。 可以执行偏置斜坡调整和偏置斜率调整以实现期望的掺杂剂分布，从而实现表面峰值掺杂剂分布和逆向掺杂剂分布。 该方法可以包括在一个实施方案中的非晶化步骤。

公开(公告)号：US07396746B2

公开(公告)日：2008-07-08

申请号：US10852643

申请日：2004-05-24

申请人： Steven R. Walther ,  Ziwei Fang ,  Justin Tocco ,  Carleton F. Ellis, III

发明人： Steven R. Walther ,  Ziwei Fang ,  Justin Tocco ,  Carleton F. Ellis, III

IPC分类号： H01L21/425

CPC分类号： H01J37/32412 ,  C23C14/48 ,  H01L21/2236

摘要： A method for plasma ion implantation of a substrate includes providing a plasma ion implantation system having a process chamber, a source for producing a plasma in the process chamber, a platen for holding a substrate in the process chamber, an anode spaced from the platen, and a pulse source for generating implant pulses for accelerating ions from the plasma into the substrate. In one aspect, a parameter of an implant process is varied to at least partially compensate for undesired effects of interaction between ions being implanted and the substrate. For example, dose rate, ion energy, or both may be varied during the implant process. In another aspect, a pretreatment step includes accelerating ions from the plasma to the anode to cause emission of secondary electrons from the anode, and accelerating the secondary electrons from the anode to a substrate for pretreatment of the substrate.

摘要翻译： 用于等离子体离子注入衬底的方法包括提供等离子体离子注入系统，其具有处理室，用于在处理室中产生等离子体的源，用于在处理室中保持衬底的压板，与压板隔开的阳极， 以及用于产生用于将离子从等离子体加速到衬底中的注入脉冲的脉冲源。 在一个方面，改变注入过程的参数以至少部分地补偿被植入的离子与衬底之间的相互作用的不期望的影响。 例如，剂量率，离子能量或二者可以在植入过程期间变化。 另一方面，预处理步骤包括将离子从等离子体加速到阳极，以引起来自阳极的二次电子的发射，以及将二次电子从阳极加速至衬底以进行预处理。

公开(公告)号：US06182604B2

公开(公告)日：2001-02-06

申请号：US09427869

申请日：1999-10-27

申请人： Matthew J. Goeckner ,  Ziwei Fang

发明人： Matthew J. Goeckner ,  Ziwei Fang

IPC分类号： C23C1600

CPC分类号： H01J37/32596 ,  C23C14/48 ,  H01J37/34 ,  H01J37/3438

摘要： A plasma doping apparatus includes a hollow cathode to increase throughput and uniformity of ion implantations in a target. The hollow cathode is located adjacent an anode and a target cathode on which a target is placed. An ionizable gas is provided in a space between the anode and the target cathode. The space in which the ionizable gas is provided is surrounded by the hollow cathode. The hollow cathode has either a circular or rectangular cross-section.

摘要翻译： 等离子体掺杂装置包括空心阴极以增加目标中的离子注入的产量和均匀性。 中空阴极位于邻近阳极和放置目标物体的目标阴极。 在阳极和目标阴极之间的空间中提供可电离气体。 可提供可离子化气体的空间被中空阴极包围。 中空阴极具有圆形或矩形横截面。

公开(公告)号：US20130017660A1

公开(公告)日：2013-01-17

申请号：US13183043

申请日：2011-07-14

申请人： Ziwei Fang ,  Ying Zhang ,  Jeff J. Xu

发明人： Ziwei Fang ,  Ying Zhang ,  Jeff J. Xu

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L21/30617 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 在一个示例中，该方法包括在衬底上形成栅极结构; 在衬底中形成掺杂区域; 执行第一蚀刻工艺以去除掺杂区域并在衬底中形成沟槽; 以及执行通过去除衬底的部分来修改沟槽的第二蚀刻工艺。

公开(公告)号：US20090283670A1

公开(公告)日：2009-11-19

申请号：US12272537

申请日：2008-11-18

申请人： Bon-Woong Koo ,  Ludovic Godet ,  Vassilis Panayotis Vourloumis ,  Vikram Singh ,  Ziwei Fang

发明人： Bon-Woong Koo ,  Ludovic Godet ,  Vassilis Panayotis Vourloumis ,  Vikram Singh ,  Ziwei Fang

IPC分类号： B01D59/44 ,  H01J49/00

CPC分类号： H01J37/32422 ,  H01J37/32935

摘要： A time-of-flight ion sensor for monitoring ion species in a plasma includes a housing. A drift tube is positioned in the housing. An extractor electrode is positioned in the housing at a first end of the drift tube so as to attract ions from the plasma. A plurality of electrodes is positioned at a first end of the drift tube proximate to the extractor electrode. The plurality of electrodes is biased so as to selectively attract ions to enter the drift tube and to drift towards a second end of the drift tube. An ion detector is positioned proximate to the second end of the drift tube. The ion detector detects arrival times associated with the at least the portion of the attracted ions.

摘要翻译： 用于监测等离子体中的离子种类的飞行时间离子传感器包括壳体。 漂移管位于外壳中。 提取器电极位于漂移管的第一端处的壳体中，以便从等离子体吸引离子。 多个电极位于漂移管的靠近提取器电极的第一端。 多个电极被偏置以选择性地吸引离子进入漂移管并漂移到漂移管的第二端。 离子检测器位于漂移管的第二端附近。 离子检测器检测与吸引的离子的至少一部分相关联的到达时间。