公开(公告)号：US06983339B1

公开(公告)日：2006-01-03

申请号：US09675801

申请日：2000-09-29

申请人： Jeffrey L. Rabe ,  Satish Acharya ,  Zohar Bogin ,  Serafin E. Garcia ,  David J. Harriman

发明人： Jeffrey L. Rabe ,  Satish Acharya ,  Zohar Bogin ,  Serafin E. Garcia ,  David J. Harriman

IPC分类号： G06F1/00

CPC分类号： G06F13/24

摘要： A method and apparatus for delivering APIC interrupts to a processor, and between processors, as FSB transactions. Interrupts and hardware signals, generated by a PCI device, are converted into an upstream memory write interrupt and further converted into an FSB interrupt transaction, received by a processor. Interrupts marked as lowest priority re-directable are redirected based on task priority information. Support for XTPR transactions to update XTPR registers is provided. Preferred ordering of XTPR update transactions and interrupts to be redirected is provided.

摘要翻译： 一种用于将APIC中断传送到处理器和处理器之间的方法和装置，作为FSB事务。 由PCI设备生成的中断和硬件信号被转换为上游存储器写入中断，并进一步转换为由处理器接收的FSB中断事务。 标记为最低优先级可重定向的中断根据任务优先级信息重定向。 提供对XTPR事务的支持以更新XTPR寄存器。 提供XTPR更新事务和重定向中断的优先顺序。

公开(公告)号：US5655127A

公开(公告)日：1997-08-05

申请号：US612673

申请日：1996-03-08

申请人： Jeffrey L. Rabe ,  Zohar Bogin ,  Ajay V. Bhatt ,  James P. Kardach ,  Nilesh V. Shah

发明人： Jeffrey L. Rabe ,  Zohar Bogin ,  Ajay V. Bhatt ,  James P. Kardach ,  Nilesh V. Shah

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  G06F1/3287 ,  Y02B60/1282 ,  Y02B60/32

摘要： A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The power consumption controller generates an interrupt signal in response to a low power event or a fully operational event. The power consumption controller also generates a clock control signal. The clock control signal is deasserted during the full-power mode of operation and alternatively asserted for a first duration and deasserted for a second duration during the low-power mode of operation. In response to an asserted clock control signal, the processor suppresses the internal clock signal to at least one functional block within the processor and in response to a deasserted clock control signal, the processor transmits the internal clock signal to at least one functional block within the processor. By transmitting the internal clock signal to at least one functional block within the processor during the low-power mode of operation, the processor may respond to communication signals from a communication device during the low-power mode of operation.

摘要翻译： 一种具有响应低功率模式和全功率工作模式的计算机系统。 计算机系统包括功率消耗控制器，处理器和通信设备。 功率消耗控制器响应于低功率事件或完全运行的事件而产生中断信号。 功耗控制器还产生时钟控制信号。 时钟控制信号在全功率工作模式期间被断言，并且在低功率操作模式期间另行断言第一持续时间并且断言第二持续时间。 响应于断言的时钟控制信号，处理器将内部时钟信号抑制到处理器内的至少一个功能块，并且响应于无效时钟控制信号，处理器将内部时钟信号发送到内部时钟信号中的至少一个功能块 处理器。 通过在低功率操作模式期间将内部时钟信号发送到处理器内的至少一个功能块，处理器可以在低功率操作模式期间响应来自通信设备的通信信号。

公开(公告)号：US07343469B1

公开(公告)日：2008-03-11

申请号：US09667050

申请日：2000-09-21

申请人： Zohar Bogin ,  Jeffrey L. Rabe

发明人： Zohar Bogin ,  Jeffrey L. Rabe

IPC分类号： G06F12/00

CPC分类号： G06F12/1009 ,  G06F12/1027

摘要： An address translation apparatus and method that can convert a limited-range memory address from a peripheral device to an expanded-range memory address on the fly. The invention can expand the limited address capability of a peripheral bus, such as a PCI bus with a 4 GB address range, to a much larger address capability, such as a 64 GB address range. This conversion can be performed on the fly by hardware, so that no appreciable delay in transfer time is created. The conversion can be performed by adding features to a conventional graphics controller interface, thus minimizing the impact on circuit complexity and system cost.

摘要翻译： 一种地址转换装置和方法，其可以将有限范围的存储器地址从外围设备转换为扩展存储器地址。 本发明可以将诸如具有4GB地址范围的PCI总线等外围总线的有限地址能力扩展到更大的地址能力，例如64GB的地址范围。 这种转换可以由硬件在飞行中执行，因此不会产生明显的传输时间延迟。 可以通过向传统图形控制器接口添加特征来实现转换，从而最小化对电路复杂性和系统成本的影响。

公开(公告)号：US5551044A

公开(公告)日：1996-08-27

申请号：US349065

申请日：1994-12-01

申请人： Nilesh V. Shah ,  Jeffrey L. Rabe ,  Zohar Bogin

发明人： Nilesh V. Shah ,  Jeffrey L. Rabe ,  Zohar Bogin

IPC分类号： G06F13/24 ,  G06F13/00

CPC分类号： G06F13/24

摘要： A circuit for controlling interrupt request signal transmission in a computer system. An input receives an interrupt request from an external component. First circuitry coupled to the input generates a signal in response to the interrupt request from the external component. The signal causes a processor to switch to fully operational mode. Second circuitry coupled to the input generates an interrupt request signal to the processor in response to the interrupt request from the external component. A signal processing circuit coupled to the second circuitry suppresses transmission of the interrupt request signal to the processor until the signal is transmitted to the processor.

摘要翻译： 用于控制计算机系统中的中断请求信号传输的电路。 输入接收来自外部组件的中断请求。 耦合到输入的第一电路响应于来自外部组件的中断请求而生成信号。 信号使处理器切换到完全运行模式。 耦合到输入的第二电路响应于来自外部组件的中断请求，向处理器生成中断请求信号。 耦合到第二电路的信号处理电路抑制中断请求信号到处理器的传输，直到信号被发送到处理器。

公开(公告)号：US20080133952A1

公开(公告)日：2008-06-05

申请号：US11633183

申请日：2006-12-04

申请人： Chai Huat Gan ,  Darren Abramson ,  Zohar Bogin

发明人： Chai Huat Gan ,  Darren Abramson ,  Zohar Bogin

IPC分类号： G06F13/00 ,  G06F1/32

CPC分类号： G06F1/3225

摘要： For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.

摘要翻译： 对于由计算机系统处理的等时数据流，例如高清晰度音频流，实施例跟踪用于数据流的输入和输出缓冲器中的可用空间。 缓冲器中的可用空间确定是否满足各种低功率进入和退出阈值。 如果满足所有低功率入口阈值，则诸如时钟，锁相环和直接介质接口链路的各种电路可能被置于低功率状态，并且数据流控制器进入空闲窗口，使得存储器请求不是 服务。 在此期间，系统DRAM可能会开始刷新。 一旦输入低功率状态，如果满足任何退出阈值，则低功率状态结束。 描述和要求保护其他实施例。

公开(公告)号：US07181605B2

公开(公告)日：2007-02-20

申请号：US10693226

申请日：2003-10-24

申请人： Zohar Bogin ,  Surya Kareenahalli ,  Anoop Mukker ,  David Sastry ,  Tuong Trieu

发明人： Zohar Bogin ,  Surya Kareenahalli ,  Anoop Mukker ,  David Sastry ,  Tuong Trieu

IPC分类号： G06F9/00

CPC分类号： G06F1/24

摘要： A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.

摘要翻译： 已经公开了响应于系统热复位来确定地关闭存储器件的方法。 该方法的一个实施例包括在系统中响应于系统中的第二类型的复位而引起系统中的多个存储器件中的第一类型的复位，如果存储器件未被初始化并且使能存储器中的确定性关断模式 控制器，其在存储器件初始化之后耦合到存储器件。 描述和要求保护其他实施例。

公开(公告)号：US07082480B2

公开(公告)日：2006-07-25

申请号：US10674944

申请日：2003-09-29

申请人： Zohar Bogin ,  Serafin E. Garcia

发明人： Zohar Bogin ,  Serafin E. Garcia

IPC分类号： G06F3/00

CPC分类号： G06F13/24 ,  G06F13/385

摘要： A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.

摘要翻译： 在具有调度器和多个下行命令队列的计算机系统中防止死锁和活动锁的技术的组合。 在一个实施例中，需要在所有受影响的下游命令队列中同时可用空间的广播事务变成延迟的事务，使得命令队列被保留，并且重试其他事务直到广播事务完成。 在另一个实施例中，如果事务在预定时间内未完成，则使用拯救计时器推迟事务。 在另一个实施例中，如果存在小于可用于该事务的预定量的下游缓冲区空间，则潜在地解决由可编程属性映射控制的存储空间的锁定事务被处理为延迟事务。

公开(公告)号：US20050195202A1

公开(公告)日：2005-09-08

申请号：US10796686

申请日：2004-03-08

申请人： David Freker ,  Aditya Sreenivas ,  Zohar Bogin ,  Anoop Mukker ,  Tuong Trieu

发明人： David Freker ,  Aditya Sreenivas ,  Zohar Bogin ,  Anoop Mukker ,  Tuong Trieu

IPC分类号： G06F12/00 ,  G06F12/14 ,  G06F13/00

CPC分类号： G06F13/1684

摘要： Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

摘要翻译： 本发明的实施例涉及使用双通道存储器件的第一通道访问第一对相邻数据块; 并且使用所述存储器件的第二通道同时访问第二对相邻数据块，所述第二对与所述第一对间隔开预定间隔。

公开(公告)号：US20050143843A1

公开(公告)日：2005-06-30

申请号：US10723132

申请日：2003-11-25

申请人： Zohar Bogin ,  Arthur Hunter ,  Krishnamurthy Venkataramana ,  Mihir Shah

发明人： Zohar Bogin ,  Arthur Hunter ,  Krishnamurthy Venkataramana ,  Mihir Shah

IPC分类号： G05B11/01 ,  G10L19/14

CPC分类号： G10L19/167

摘要： Machine-readable media, methods, and apparatus are described to pace commands to codecs. Some embodiments comprise an audio controller that transfers frames to codecs and places commands in the frames at a pace dictated by a command pacer.

摘要翻译： 描述了机器可读介质，方法和装置，以将命令调整到编解码器。 一些实施例包括音频控制器，该音频控制器将帧传送到编解码器，并以由命令起搏器指示的速度将命令放置在帧中。

公开(公告)号：US20050114569A1

公开(公告)日：2005-05-26

申请号：US10723347

申请日：2003-11-25

申请人： Zohar Bogin ,  Brent Chartrand ,  Arthur Hunter

发明人： Zohar Bogin ,  Brent Chartrand ,  Arthur Hunter

IPC分类号： G06F13/16 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： Machine-readable media, methods, and apparatus are described to stream data between a codec and a buffer in system memory and to maintain a value in system memory that is indicative of a current position in the buffer. In some embodiments, an audio controller streams the data across an isochronous channel having relaxed ordering rules to the buffer in the system memory and updates the value indicative of current position via a write across the isochronous channel to the system memory.

摘要翻译： 描述了机器可读介质，方法和装置，以在系统存储器中的编解码器和缓冲器之间流式传输数据，并维持指示缓冲器中当前位置的系统存储器中的值。 在一些实施例中，音频控制器通过具有放松排序规则的同步信道将数据流传输到系统存储器中的缓冲器，并且通过跨同步信道的写入更新指示当前位置的值到系统存储器。