公开(公告)号：US09344208B2

公开(公告)日：2016-05-17

申请号：US13593370

申请日：2012-08-23

申请人： Med Belhadj ,  Hojjat Salemi

发明人： Med Belhadj ,  Hojjat Salemi

IPC分类号： H04J3/06 ,  H04L12/28

CPC分类号： H04J3/0667 ,  H04J3/065 ,  H04J2203/0089

摘要： Systems and methods for performing timing offset and or fractional frequency offset for the purpose of time and/or frequency synchronization are provided. Timing packets are exchanged between a master device and a slave device. In addition, timing adjustment information is received by the slave device. The slave device uses the timing adjustment information in conjunction with the transmit and receive times for the timing packets to estimate at timing offset and/or fractional frequency offset.

摘要翻译： 提供了用于为时间和/或频率同步的目的执行定时偏移和/或分数频率偏移的系统和方法。 定时分组在主设备和从设备之间交换。 此外，从设备接收定时调整信息。 从设备使用定时调整信息结合定时分组的发送和接收时间在定时偏移和/或分数频率偏移处进行估计。

公开(公告)号：US09075607B2

公开(公告)日：2015-07-07

申请号：US13935092

申请日：2013-07-03

申请人： CORTINA SYSTEMS, INC.

发明人： Fredrik Olsson ,  Shawn Lawrence Scouten ,  Ryan Patrick Donohue

IPC分类号： G06F1/32 ,  H04L12/12

CPC分类号： G06F1/3281 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/3234 ,  G06F1/3278 ,  G06F1/3287 ,  G06F1/3293 ,  H04L12/12 ,  Y02D10/157 ,  Y02D10/171 ,  Y02D50/20 ,  Y02D50/40 ,  Y02D50/42

摘要： Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states.

摘要翻译： 公开了与数据接口功耗控制相关的装置和技术。 在数据传输模块不用于传输数据的时候，数据传输模块的组件可以在其正常操作状态和降低的功率状态之间选择性地移动。 关于要移动到其降低功率状态的特定组件的决定可以基于组件的各自的定时特性和/或组件的各自的功率消耗特性。 在一些实施例中，当数据传输模块的正常操作要恢复时，可以执行动作以减少数据传输模块的加电时间。 在具有用于每个连接的相应数据传输模块的多连接接口的情况下，可以通过将数据传输模块的子集移动到降低的功率状态来部分地关闭接口。

公开(公告)号：US20140181319A1

公开(公告)日：2014-06-26

申请号：US14135111

申请日：2013-12-19

申请人： CORTINA SYSTEMS, INC.

发明人： Charles Chen ,  Ryan Patrick Donohue ,  Donggun Keung ,  Xi Chen ,  Xiaochong Cao ,  Zeineddine Chair

IPC分类号： H04L12/801

CPC分类号： H04L47/33 ,  G06F13/385 ,  H04L69/08 ,  H04L69/12 ,  H04L69/321

摘要： Communication traffic processing architectures and methods are disclosed. Processing load on main Central Processing Units (CPUs) can be alleviated by offloading data processing tasks to separate hardware.

摘要翻译： 公开了通信业务处理架构和方法。 通过将数据处理任务卸载到单独的硬件，可以缓解主要中央处理单元（CPU）的处理负载。

公开(公告)号：US20140053039A1

公开(公告)日：2014-02-20

申请号：US14066332

申请日：2013-10-29

申请人： Cortina Systems, Inc.

发明人： Arash Farhoodfar ,  Frank R. Kschischang ,  Benjamin P. Smith ,  Andrew Hunt

IPC分类号： H03M13/27

CPC分类号： H03M13/2778 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/2742 ,  H03M13/2757 ,  H03M13/2767 ,  H03M13/2782 ,  H03M13/6502 ,  H04L1/0071

摘要： Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.

摘要翻译： 各个不同维度的多个数据置换操作被用于使用比在单个置换操作中直接实现整体置换时使用的每个置换中更小的数据块来提供整体有效的数据置换。 在一个置换操作中已被置换的数据被块交织，并且随后的置换操作中交错的数据被置换。 矩阵转置是可以在置换操作之间应用的块交织的一个示例。

公开(公告)号：US08384452B1

公开(公告)日：2013-02-26

申请号：US13231798

申请日：2011-09-13

申请人： Kevin Parker ,  Malcolm Stevens ,  Stephane Dallaire ,  Shawn Scouten ,  Jeff P. Kirsten

发明人： Kevin Parker ,  Malcolm Stevens ,  Stephane Dallaire ,  Shawn Scouten ,  Jeff P. Kirsten

IPC分类号： H03L7/06

CPC分类号： H03L7/23 ,  H03L7/07 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/18 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

摘要： A phase difference between a reference clock signal and a feedback signal is digitally detected. A resultant phase detection signal is digitally filtered, and a PLL (Phase Locked Loop) output signal is synthesized in a fractional synthesizer under control of the digitally filtered phase detection signal. A feedback path, which could include an integer divider and/or a fractional N divider, provides the feedback signal based on the PLL output signal. The combination of a wide bandwidth fractional synthesizer and a low bandwidth digital PLL provides for a low bandwidth jitter filtering function with a wide bandwidth PLL to suppress VCO (Voltage Controlled Oscillator) noise and crosstalk.

摘要翻译： 数字检测参考时钟信号和反馈信号之间的相位差。 合成相位检测信号被数字滤波，并且在数字滤波相位检测信号的控制下，在分数合成器中合成PLL（锁相环）输出信号。 可以包括整数分频器和/或分数N分频器的反馈路径基于PLL输出信号提供反馈信号。 宽带分数合成器和低带宽数字PLL的组合提供了具有宽带宽PLL的低带宽抖动滤波功能，以抑制VCO（压控振荡器）噪声和串扰。

公开(公告)号：US20130039182A1

公开(公告)日：2013-02-14

申请号：US13208304

申请日：2011-08-11

申请人： Abhimanyu Das ,  Eugene Lee ,  Deyi Dong ,  Dongsheng Zhang

发明人： Abhimanyu Das ,  Eugene Lee ,  Deyi Dong ,  Dongsheng Zhang

IPC分类号： H04L12/24 ,  H04J14/00 ,  H04L12/26

CPC分类号： H04L41/0816 ,  H04L47/14 ,  H04Q11/0067 ,  H04Q2011/0064

摘要： There are disclosed systems and methods for detecting and controlling congestion in an Optical Line Terminal (OLT). The OLT has a plurality of ports. Each port of the plurality of ports communicates with at least one Optical Network Unit (ONU), and each port of the plurality of ports has a respective enforced maximum upstream bandwidth. For example, the maximum upstream bandwidth may be enforced by a Dynamic Bandwidth Allocation (DBA) algorithm. The OLT further includes an uplink port through which data received from each of the plurality of ports are transmitted. In one embodiment, if there is congestion of the data at the uplink port, then the enforced maximum upstream bandwidth for at least one port of the plurality of ports is modified.

摘要翻译： 公开了用于在光线路终端（OLT）中检测和控制拥塞的系统和方法。 OLT具有多个端口。 多个端口的每个端口与至少一个光网络单元（ONU）通信，并且多个端口的每个端口具有相应的强制最大上行带宽。 例如，最大上行带宽可以通过动态带宽分配（DBA）算法来实现。 OLT还包括上行链路端口，通过该上行链路端口从多个端口中的每一个接收的数据被发送。 在一个实施例中，如果在上行链路端口处存在数据拥塞，则修改多个端口中至少一个端口的强制最大上行带宽。

公开(公告)号：US20120137157A1

公开(公告)日：2012-05-31

申请号：US13363129

申请日：2012-01-31

申请人： Fredrik Olsson ,  Shawn Lawrence Scouten ,  Ryan Patrick Donohue

发明人： Fredrik Olsson ,  Shawn Lawrence Scouten ,  Ryan Patrick Donohue

IPC分类号： G06F1/32

CPC分类号： G06F1/3281 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/3234 ,  G06F1/3278 ,  G06F1/3287 ,  G06F1/3293 ,  H04L12/12 ,  Y02D10/157 ,  Y02D10/171 ,  Y02D50/20 ,  Y02D50/40 ,  Y02D50/42

摘要： Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states.

摘要翻译： 公开了与数据接口功耗控制相关的装置和技术。 在数据传输模块不用于传输数据的时候，数据传输模块的组件可以在其正常操作状态和降低的功率状态之间选择性地移动。 关于要移动到其降低功率状态的特定部件的决定可以基于组件的各自的定时特性和/或组件的各自的功率消耗特性。 在一些实施例中，当数据传输模块的正常操作要恢复时，可以执行动作以减少数据传输模块的加电时间。 在具有用于每个连接的相应数据传输模块的多连接接口的情况下，可以通过将数据传输模块的子集移动到降低的功率状态来部分地关闭接口。

公开(公告)号：US07327760B1

公开(公告)日：2008-02-05

申请号：US09976310

申请日：2001-10-12

申请人： Bidyut Parruck ,  Chulanur Ramakrishnan

发明人： Bidyut Parruck ,  Chulanur Ramakrishnan

IPC分类号： H04L12/56

CPC分类号： H04L49/602 ,  H04L49/30 ,  H04L2012/5605 ,  H04L2012/5652 ,  H04L2012/5667

摘要： A multi-service segmentation and reassembly (MS-SAR) integrated circuit is disposed on a line card in a router or switch. The MS-SAR can operate in an ingress mode so that it receives packet and/or cell format data and forwards that data to either a packet-based or a cell-based switch fabric. The MS-SAR can also operate in an egress mode so that it receives data from either a packet-based or a cell-based switch fabric and outputs that data in packet and/or cell format. The MS-SAR has a data path through which many flows of different traffic types are processed simultaneously. Each flow is processed by functional blocks along the data path in accordance with one of several application types, the application type for a flow being predetermined by the host processor of the router or switch. Segmentation, reassembly and partitioning techniques are disclosed that reduce costs and facilitate high-speed operation.

摘要翻译： 在路由器或交换机的线路卡上设置多业务分段和重组（MS-SAR）集成电路。 MS-SAR可以以入口模式操作，以便它接收分组和/或小区格式数据，并将该数据转发到基于分组或基于小区的交换结构。 MS-SAR还可以以出口模式操作，从而从基于分组或基于小区的交换结构接收数据，并以分组和/或小区格式输出该数据。 MS-SAR具有数据路径，同时处理不同流量类型的许多流。 根据多个应用类型之一，沿着数据路径的功能块处理每个流程，流程的应用类型由路由器或交换机的主机处理器预先确定。 公开了降低成本并促进高速运行的分段，重组和分区技术。

公开(公告)号：US07095760B1

公开(公告)日：2006-08-22

申请号：US09539461

申请日：2000-03-30

申请人： Bidyut Parruck ,  Joseph A. Nguyen ,  Chulanur Ramakrishnan

发明人： Bidyut Parruck ,  Joseph A. Nguyen ,  Chulanur Ramakrishnan

IPC分类号： H04J3/02

CPC分类号： H04L12/5601 ,  H04L2012/5605 ,  H04L2012/5652 ,  H04L2012/5665

摘要： A technique for disguising ATM cells as ATM cell-containing packets within a routing facility to permit the packet-only switch to also handle switching of the ATM cells. The technique has wide applications within the backbone infrastructure, Wide Area Networks, Metro Area Networks, Local Area Networks, and particularly within a routing facility to handle high speed traffic. The technique can receive both ATM cells and packets for switching via a single channel or optical fiber or receive ATM cells and packets via two separate channels or two separate fibers. The ability to handle both ATM cell and packet switching allows packet-only routers to handle ATM traffic, thereby reducing the cost of the switching infrastructure for network operators.

摘要翻译： 一种用于将ATM信元伪装成路由设施内的含有ATM信元的分组的技术，以允许仅分组交换机也处理ATM信元的切换。 该技术在骨干基础设施，广域网，城域网，局域网内具有广泛的应用，特别是在处理高速业务的路由设施中。 该技术可以接收ATM信元和分组，用于通过单个信道或光纤进行交换，或者经由两个分离的信道或两个分离的光纤接收ATM信元和数据包。 处理ATM信元和分组交换两者的能力允许仅数据包路由器处理ATM流量，从而降低网络运营商的交换基础架构的成本。

公开(公告)号：US09515854B2

公开(公告)日：2016-12-06

申请号：US14754038

申请日：2015-06-29

申请人： CORTINA SYSTEMS, INC.

发明人： Shawn Lawrence Scouten

IPC分类号： H03K3/00 ,  H04L25/02

CPC分类号： H04L25/0276 ,  H04L25/0292

摘要： An AC coupling circuit is provided that has a level shifter circuit having a p input voltage and an n input voltage and producing a p output voltage and a p output voltage. There is a common mode voltage adjustment feedback circuit configured to cause a common mode voltage output to tend towards a specified reference voltage, the common mode voltage output being an average of the p output and n output voltages of the level shifter circuit. In combination, the level shifter circuit and the feedback circuit allow the interconnection of a first circuit that operates at a first, unspecified, common mode voltage to be connected to a second circuit having a required common mode voltage. The level shifter may be formed of adjustable components such that the frequency response of the level shifter circuit can be adjusted to compensate for a frequency response of an interconnect between the first circuit and the second circuit.