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1.发明授权Current controlled biasing for current-steering based RF variable gain amplifiers 有权基于电流导向的RF可变增益放大器的电流控制偏置公开(公告)号：US08270917B2
公开(公告)日：2012-09-18
申请号：US12520513
申请日：2007-12-20
IPC分类号： H04B1/04
CPC分类号： H03G3/3042 , H03G1/04
摘要： An adaptive current control circuit for reduced power consumption and minimized gain shift in a variable gain amplifier. An automatic gain control circuit provides gain control voltages in response to a gain control signal. The gain control voltages are used by the variable gain amplifier to set the gain of the output signal for wireless transmit operations. The adaptive current control circuit receives the same gain control voltages for reducing current to the variable gain amplifier during low gain operation, while providing higher currents during high gain operation. The current that is provided is a hybrid mix of proportional to absolute temperature (PTAT) current and complementary to absolute temperature (CTAT) current for minimizing temperature effects on the gain. The ratio of PTAT current and CTAT current is adjustable for specific temperature ranges to further minimize temperature effects on the gain.
摘要翻译： 一种自适应电流控制电路，用于降低可变增益放大器的功耗和最小化增益偏移。 自动增益控制电路响应增益控制信号提供增益控制电压。 可变增益放大器使用增益控制电压来设置无线发射操作的输出信号的增益。 自适应电流控制电路在低增益操作期间接收相同的增益控制电压，以减小电流到可变增益放大器，同时在高增益操作期间提供更高的电流。 提供的电流是与绝对温度（PTAT）电流成比例和与绝对温度（CTAT）电流互补的混合混合，以最小化对增益的温度影响。 PTAT电流和CTAT电流的比例可针对特定温度范围进行调节，以进一步降低温度对增益的影响。
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公开(公告)号：US20100124260A1
公开(公告)日：2010-05-20
申请号：US12598715
申请日：2008-05-05
CPC分类号： H04B1/40
摘要： Peripheral components of a wireless radio system can be controlled by a wireless transceiver. The transceiver stores parallel or serial bit patterns in memory, each bit pattern corresponding to a particular control configuration for one or more peripheral components. A further control device, such as baseband controller, issues an address corresponding to the desired functional operation of the peripheral components to the transceiver. A memory sub-system of the transceiver uses the address to output the appropriate bit pattern. The bit pattern can be provided in parallel to statically control individual control lines, or can be converted into a serial bitstream decodable by a command decoder. The command decoder can then decode the bitstream and locally issue the appropriate control signals for the peripheral components.
摘要翻译： 无线无线电系统的外围组件可以由无线收发器控制。 收发器将并行或串行位模式存储在存储器中，每个位模式对应于一个或多个外围组件的特定控制配置。 诸如基带控制器的另外的控制装置向收发器发出与周边组件的所需功能操作相对应的地址。 收发器的存储器子系统使用地址输出适当的位模式。 可以并行提供位模式以静态控制单独的控制线，或者可以将其转换为由命令解码器解码的串行比特流。 命令解码器然后可以对比特流进行解码，并且在本地发出适用于外围组件的控制信号。
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公开(公告)号：US07715814B2
公开(公告)日：2010-05-11
申请号：US11569031
申请日：2005-05-13
申请人： Tajinder Manku , Masoud Kahrizi
发明人： Tajinder Manku , Masoud Kahrizi
CPC分类号： H04B1/30 , H03D7/00 , H04B15/06 , H04B2215/065
摘要： A method and system for dynamically shifting spurious tones away from the desired frequency in a virtual local oscillator receiver, such that any undesired signal residing at such spurious tones are effectively delineated from the desired signal and removed from the RF input signal. The system detects the presence of potential undesired blocker signals in the RF input signal, and initiates an iterative power comparison and mixer signal adjustment loop. As the virtual local oscillator uses two mixer signals, the frequency of one of the mixer signals is adjusted during the loop until the power of the down-converted signal is minimized to a predetermined level. Minimized power in the down-converted signal is indicative of the absence of the blocker signal, since the presence of a relatively high power signal is indicative of a blocker signal overlapping with a desired signal.
摘要翻译： 一种用于在虚拟本地振荡器接收机中动态地将杂散音调从期望频率移位的方法和系统，使得驻留在这种寄生音调处的任何不需要的信号被有效地从期望的信号中描绘出并从RF输入信号中去除。 该系统检测RF输入信号中存在潜在的不希望的阻塞信号，并启动迭代功率比较和混频信号调节环路。 由于虚拟本地振荡器使用两个混频器信号，所以在环路中调整混频信号之一的频率，直到下变频信号的功率被最小化到预定的电平。 下变频信号中的最小化功率表示不存在阻塞信号，因为相对高功率信号的存在表示阻塞信号与期望信号重叠。
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公开(公告)号：US20100060333A1
公开(公告)日：2010-03-11
申请号：US12515562
申请日：2007-12-13
申请人： Tajinder Manku , Christopher Snyder
发明人： Tajinder Manku , Christopher Snyder
IPC分类号： H03L7/06
摘要： A digital phase lock loop (PLL) circuit having a digital charge pump circuit for providing digital signals corresponding to a difference in phase between an internal clock corresponding to a voltage controlled oscillator, and a reference clock. These digital signals are processed by a digital processing circuit for providing digital control signals. Some of the digital control signals are converted into an analog control signal to provide fine control of the voltage controlled oscillator, while the remaining digital control signals provide coarse control of the voltage controlled oscillator.
摘要翻译： 一种具有数字电荷泵电路的数字锁相环（PLL）电路，用于提供对应于与压控振荡器相对应的内部时钟之间的相位差的数字信号和参考时钟。 这些数字信号由用于提供数字控制信号的数字处理电路处理。 一些数字控制信号被转换成模拟控制信号以提供压控振荡器的精细控制，而剩余的数字控制信号提供压控振荡器的粗略控制。
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公开(公告)号：US08509290B2
公开(公告)日：2013-08-13
申请号：US12520448
申请日：2007-12-21
IPC分类号： H04B1/38
CPC分类号： H03G3/3047 , H04B2001/0416
摘要： A closed loop power output calibration system for variable power output wireless devices. The wireless device includes a wireless transceiver having a transmit core coupled to a discrete power amplifier. Power detection circuitry formed in the wireless transceiver provides a detected power level of the power amplifier, and a reference power level, both of which are converted to digital signals using existing I and Q signal analog to digital converters in the receiver core. The digital signals are processed to cancel power distortion and temperature effects to provide a resulting power feedback signal. Corrective control signals are generated in response to the power feedback signal relative to a desired power output level. The gain in the transmit core is then adjusted in response to the corrective control signals such that the power amplifier outputs the target output power level.
摘要翻译： 一种用于可变功率输出无线设备的闭环功率输出校准系统。 无线设备包括具有耦合到分立功率放大器的发射芯的无线收发器。 在无线收发器中形成的功率检测电路提供功率放大器的检测功率电平和参考功率电平，两者都使用接收机核心中现有的I和Q信号模数转换器转换成数字信号。 处理数字信号以消除功率失真和温度影响，以提供最终的功率反馈信号。 响应于功率反馈信号相对于期望的功率输出电平产生校正控制信号。 然后响应于校正控制信号调整发送内核中的增益，使得功率放大器输出目标输出功率电平。
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公开(公告)号：US08004326B2
公开(公告)日：2011-08-23
申请号：US12515562
申请日：2007-12-13
申请人： Tajinder Manku , Christopher Snyder
发明人： Tajinder Manku , Christopher Snyder
IPC分类号： H03L7/06
摘要： A digital phase lock loop (PLL) circuit having a digital charge pump circuit for providing digital signals corresponding to a difference in phase between an internal clock corresponding to a voltage controlled oscillator, and a reference clock. These digital signals are processed by a digital processing circuit for providing digital control signals. Some of the digital control signals are converted into an analog control signal to provide fine control of the voltage controlled oscillator, while the remaining digital control signals provide coarse control of the voltage controlled oscillator.
摘要翻译： 一种具有数字电荷泵电路的数字锁相环（PLL）电路，用于提供对应于与压控振荡器相对应的内部时钟之间的相位差的数字信号和参考时钟。 这些数字信号由用于提供数字控制信号的数字处理电路处理。 一些数字控制信号被转换成模拟控制信号以提供压控振荡器的精细控制，而剩余的数字控制信号提供压控振荡器的粗略控制。
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公开(公告)号：US07742747B2
公开(公告)日：2010-06-22
申请号：US11626964
申请日：2007-01-25
CPC分类号： H04B1/12 , H03D2200/0045 , H04B17/21
摘要： An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.
摘要翻译： 公开了一种用于无线收发器的综合自动IIP2校准架构。 该架构使得无线收发器能够生成具有最小附加电路的具有二阶音调的测试射频（RF）信号。 特别地，使用本机收发器电路和测试适配器电路的组合产生测试RF信号。 本地收发器电路是在收发器芯片上实现的用于在正常操作期间执行本机收发器功能的那些电路，其可用于产生测试（RF）信号。 测试适配器电路被添加到收发器芯片中，更具体地被添加到本地电路，用于使得本机电路能够以自测试操作模式生成测试RF信号。 用于实现特定的IIP2最小化方案的电路可以在自检操作模式下在收发器芯片中包括在自动IIP2校准中。
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公开(公告)号：US07710185B2
公开(公告)日：2010-05-04
申请号：US11569021
申请日：2005-05-12
申请人： Tajinder Manku
发明人： Tajinder Manku
CPC分类号： H03K5/1252 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03F1/3211 , H03F1/3223 , H03F3/24 , H03F3/45183 , H03F2200/372 , H03F2200/87 , H03F2203/45318 , H03F2203/45366 , H03F2203/45498 , H03F2203/45544 , H03K5/02 , H04B1/0475 , H04B1/123 , H04B2001/0441
摘要： A CMOS transconductor for cancelling third-order intermodulation is provided. The transconductor includes a transconductance circuit and a tuneable distortion circuit. The transconductance circuit takes an input voltage and generates an output current having a transconductance element and an IM3 element. The distortion circuit takes the same input voltage and generates a current having an IM3 element of equal amplitude and opposite phase to the IM3 element of the transconductance circuit. A controller circuit tunes the distortion circuit to adjust its IM3 element to substantially equal the amplitude of the IM3 of the transconductance circuit. The distortion and transconductance circuits are arranged to sum their output currents thereby effectively cancelling the IM3 elements, leaving the transconductance relatively unmodified.
摘要翻译： 提供了用于消除三阶互调的CMOS跨导体。 跨导体包括跨导电路和可调谐失真电路。 跨导电路采用输入电压并产生具有跨导元件和IM3元件的输出电流。 失真电路采用相同的输入电压，并产生具有与跨导电路的IM3元件相等幅度和相反相位的IM3元件的电流。 控制器电路调谐失真电路以将其IM3元件调整为基本上等于跨导电路的IM3的振幅。 失真和跨导电路被布置为对其输出电流求和，从而有效地消除IM3元件，从而使跨导相对未被修改。
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公开(公告)号：US08451881B2
公开(公告)日：2013-05-28
申请号：US12598715
申请日：2008-05-05
IPC分类号： H04B1/38
CPC分类号： H04B1/40
摘要： Peripheral components of a wireless radio system can be controlled by a wireless transceiver. The transceiver stores parallel or serial bit patterns in memory, each bit pattern corresponding to a particular control configuration for one or more peripheral components. A further control device, such as baseband controller, issues an address corresponding to the desired functional operation of the peripheral components to the transceiver. A memory sub-system of the transceiver uses the address to output the appropriate bit pattern. The bit pattern can be provided in parallel to statically control individual control lines, or can be converted into a serial bitstream decodable by a command decoder. The command decoder can then decode the bitstream and locally issue the appropriate control signals for the peripheral components.
摘要翻译： 无线无线电系统的外围组件可以由无线收发器控制。 收发器将并行或串行位模式存储在存储器中，每个位模式对应于一个或多个外围组件的特定控制配置。 诸如基带控制器的另外的控制装置向收发器发出与周边组件的所需功能操作相对应的地址。 收发器的存储器子系统使用地址输出适当的位模式。 可以并行提供位模式以静态控制单独的控制线，或者可以将其转换为由命令解码器解码的串行比特流。 命令解码器然后可以对比特流进行解码，并且在本地发出适用于外围组件的控制信号。
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10.发明授权System for reducing second order intermodulation products from differential circuits 有权用于从差分电路减少二阶互调产物的系统公开(公告)号：US07554380B2
公开(公告)日：2009-06-30
申请号：US11298667
申请日：2005-12-12
IPC分类号： G06G7/16
CPC分类号： H03D7/1441 , H03D7/1433 , H03D7/1458 , H03D7/1466 , H03D2200/0047 , H03D2200/0088
摘要： A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated. The switching transistors of the mixer circuit can be maintained at minimal dimensions to reduce switching signal drive loading, resulting in lower power consumption and higher operating frequencies than if larger switching transistors were used.
摘要翻译： 一种具有用于平衡两个输出路径的电气特性的失配校正电路的无源CMOS差分混频器电路。 一旦差分电路的输出路径平衡或尽可能匹配，可以抑制二阶互调乘积的产生或至少降低到可接受的水平。 失配校正电路接收数字偏移信号，并产生一个或多个电压信号以选择性地施加到无源差分混频器电路的信号路径。 电压信号可以调节施加到所选晶体管的体积端子的反向栅极偏置电压以调整其阈值电压，或者可以将电压信号调整为直接施加到选定信号路径的共模电压。 由于差分混频器电路是无源的，所以不产生直流电流对噪声的贡献。 混合电路的开关晶体管可以维持在最小的尺寸以减少开关信号驱动负载，导致比使用更大的开关晶体管时更低的功耗和更高的工作频率。
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