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3347 条记录 (耗时 0.036 秒)

    AMPLIFIER WITH CASCODE ARRANGEMENT
    3.
    发明公开
    AMPLIFIER WITH CASCODE ARRANGEMENT 审中-公开

    公开(公告)号：US20240364277A1

    公开(公告)日：2024-10-31

    申请号：US18309558

    申请日：2023-04-28

    申请人： NXP USA, Inc.

    发明人： David Edward Bien ,  Xu Jason Ma

    IPC分类号： H03F1/52 ,  H03F3/04

    CPC分类号： H03F1/52 ,  H03F3/04 ,  H03F2200/426

    摘要： An amplifier device, such as an operational amplifier device or unity gain buffer, may include a first input terminal, an inverting input terminal, a non-inverting input terminal, a reference voltage supply terminal, a negative voltage supply terminal, and an output terminal. The amplifier device may include one or more cascode arrangements, such as a first cascode arrangement coupled between the negative voltage supply terminal and the output terminal. A first transistor of the first cascode stage may be configured to receive a variable bias voltage at its gate terminal. A second transistor of the first cascode stage may be configured to receive a fixed bias voltage at its gate terminal. The variable bias voltage may correspond to a first input voltage supplied at the first input terminal.

    Circuits for inverters and pull-up/pull-down circuits
    4.
    发明授权
    Circuits for inverters and pull-up/pull-down circuits 有权

    公开(公告)号：US12132480B2

    公开(公告)日：2024-10-29

    申请号：US18160605

    申请日：2023-01-27

    申请人： NXP USA, INC.

    发明人： Pascal Kamel Abouda ,  Badr Guendouz ,  Hiba Mediouni

    IPC分类号： H03K19/003

    CPC分类号： H03K19/00315

    摘要： A circuit is disclosed, comprising: an inverter comprising first and second inverter transistors, each having: a gate terminal connected in common to a drive node, a source terminal, connected to respective first and second voltage rails, and a drain terminal connected to a common first resistor, wherein an inverter output node is connected between the first resistor and the drain terminal of a shorting one of the transistors; a tying transistor connected between the drive node and the voltage rails to which the shorting transistor is connected; a biasing circuit connected to the tying transistor's control terminal and configured to be controlled by a local drive signal and bias the tying transistor control terminal to a voltage such that the tying transistor ties the drive node of the relevant voltage rail in response to the drive signal having a first state; and a circuit for providing the local drive signal.

    T-match topology with baseband termination
    5.
    发明授权
    T-match topology with baseband termination 有权

    公开(公告)号：US12132453B2

    公开(公告)日：2024-10-29

    申请号：US17471228

    申请日：2021-09-10

    申请人： NXP USA, Inc.

    发明人： Jeffrey Spencer Roberts ,  Ning Zhu ,  Damon G. Holmes

    IPC分类号： H03F3/195 ,  H03F1/02 ,  H03F1/56

    CPC分类号： H03F1/565 ,  H03F1/0288 ,  H03F3/195 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451

    摘要： Embodiments of RF amplifiers and packaged RF amplifier devices each include an amplification path with a transistor die, and an output-side impedance matching circuit having a T-match circuit topology. The output-side impedance matching circuit includes a first inductive element connected between the transistor output terminal and a quasi RF cold point node, a second inductive element connected between the quasi RF cold point node and an output of the amplification path, and a first capacitance connected between the quasi RF cold point node and a ground reference node. The RF amplifiers and devices also include a baseband termination circuit connected to the quasi RF cold point node, which includes a third inductive element, a resistor, and a second capacitance in series between the quasi RF cold point node and the ground reference node and a third capacitance between a baseband termination circuit node and the ground reference node.

    Method and apparatus for multi-link communications
    7.
    发明授权
    Method and apparatus for multi-link communications 有权

    公开(公告)号：US12127254B2

    公开(公告)日：2024-10-22

    申请号：US17488084

    申请日：2021-09-28

    申请人： NXP USA, Inc.

    发明人： Young Hoon Kwon ,  Liwen Chu ,  Hongyuan Zhang

    IPC分类号： H04W4/00 ,  H04W48/16 ,  H04W74/0816

    CPC分类号： H04W74/0816 ,  H04W48/16

    摘要： Embodiments of a method and an apparatus for multi-link communications are disclosed. In an embodiment, a method for multi-link communications involves announcing, by a non-access point (non-AP) multi-link device (MLD) to an access point (AP) MLD, a frame exchange restriction in an enhanced multi-link operation, receiving, by the AP MLD from the non-AP MLD, the frame exchange restriction, and transmitting, by the AP MLD to the non-AP MLD, an initial frame according to the frame exchange restriction.

    Very low voltage I/O circuit and method for screening defects
    8.
    发明授权
    Very low voltage I/O circuit and method for screening defects 有权

    公开(公告)号：US12126334B2

    公开(公告)日：2024-10-22

    申请号：US17960078

    申请日：2022-10-04

    申请人： NXP USA, Inc.

    发明人： Hector Sanchez ,  Thomas Henry Luedeke ,  Stephen Robert Traynor

    IPC分类号： H03K17/687 ,  H03K19/0185 ,  H03K19/20

    CPC分类号： H03K17/6872 ,  H03K19/018521 ,  H03K19/20

    摘要： A GPIO includes a transmitter having an output stage connected to the I/O pad and adapted to supply transmit data to an I/O pad in response to output data generated by a low voltage core logic operating within a functional voltage range for transmit operations; a receiver adapted to supply receive data to the low voltage core logic operating within the functional voltage range in response to input data received at the I/O pad for receive operations; a VLV transmitter adapted to supply VLV transmit data to the output stage of the transmitter and not directly to the I/O pad in response to output test data generated by the low voltage core logic; and a VLV receiver adapted to supply VLV receive data to the low voltage core logic operating within a low core supply voltage range in response to input data received from the output stage of the transmitter.