公开(公告)号：US20120235704A1

公开(公告)日：2012-09-20

申请号：US13487100

申请日：2012-06-01

申请人： Tony Yeung ,  Michael Y. Zhang

发明人： Tony Yeung ,  Michael Y. Zhang

IPC分类号： H03K17/16

CPC分类号： H04L25/0278 ,  H03K19/0005 ,  H04B3/36 ,  H04L25/0272 ,  H04L25/0286 ,  H04L25/029 ,  H04L25/0298 ,  H04L25/03878

摘要： A redriver chip is inserted between a transmitter chip and a receiver chip and re-drives differential signals from the transmitter chip to the receiver chip. The redriver chip has switched output termination that switches to a high value to detect far-end termination at the receiver chip, and to a low value for signaling. An output detector detects when the receiver chip has termination to ground and enables switched input termination to provide termination to ground on the lines back to the transmitter chip so that the far-end termination on the receiver chip is mirrored back to the transmitter chip, hiding the redriver chip. An input signal detector detects when the transmitter chip begins signaling and enables an equalizer, limiter, pre-driver, and output stage to re-drive the signals to the receiver chip. The input signal detector also causes the switched output termination to switch to the low value termination for signaling.

摘要翻译： 转发器芯片插入在发射机芯片和接收器芯片之间，并将差分信号从发射机芯片重新驱动到接收器芯片。 转接芯片已切换输出端接，切换到高电平值，以检测接收芯片的远端终端，并发送信号低值。 输出检测器检测接收器芯片何时终止接地并使能切换输入端接，以将线路上的终端提供给发射机芯片，使得接收器芯片上的远端终端被镜像回发射机芯片，隐藏 转盘芯片。 输入信号检测器检测发射机芯片什么时候开始发信号，并启用均衡器，限幅器，预驱动器和输出级，以将信号重新驱动到接收器芯片。 输入信号检测器还使切换输出端接切换到低值终端用于信令。

公开(公告)号：US07332977B2

公开(公告)日：2008-02-19

申请号：US11306262

申请日：2005-12-21

申请人： Boris Drakhlis ,  Wing Faat Liu ,  Craig M. Taylor ,  Tony Yeung

发明人： Boris Drakhlis ,  Wing Faat Liu ,  Craig M. Taylor ,  Tony Yeung

IPC分类号： H03B27/00

CPC分类号： H03B5/36 ,  H03B5/06 ,  H03B5/364 ,  H03B2200/0008 ,  H03B2200/007 ,  H03B2200/0098

摘要： A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc1)×(Xc2) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc1 and Xc2 are the effective capacitive reactances of phase-shift legs at nodes X1 and X2. The third overtone is doubled by a multiplier and the final output filtered to remove the third overtone and select a frequency six times the fundamental frequency. A pair of Colpitts or Pierce amplifier half circuits is attached to the phase-shift leg nodes. The leg nodes can be capacitively isolated from Pierce-amplifier circuit nodes to improve start-up. Frequency doubling can be performed by summing currents from the two oscillator half circuits.

摘要翻译： 晶体振荡器在晶体的基频的第三个泛音下工作。 选择两个相移支路节点之间的分流电阻的值，使得乘积gmx（Xc 1）x（Xc 2）的绝对值大于晶体的有效电抗，其中gm是 附接到相移支脚的放大器，Xc 1和Xc 2是节点X 1和X 2处的相移支脚的有效容抗。 乘法器将第三个泛音加倍，滤波后的最终输出消除第三个泛音，并选择六倍于基频的频率。 一对Colpitts或Pierce放大器半电路连接到相移腿节点。 腿节点可以与Pierce放大器电路节点电容性隔离，以提高启动能力。 可以通过对来自两个振荡器半电路的电流求和来执行倍频。

公开(公告)号：US06867957B1

公开(公告)日：2005-03-15

申请号：US10065364

申请日：2002-10-09

申请人： Paul C. F. Tong ,  Ming-Dou Ker ,  Ping Ping Xu

发明人： Paul C. F. Tong ,  Ming-Dou Ker ,  Ping Ping Xu

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0262 ,  H01L27/0266

摘要： Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source/drain node between the two cascaded transistors is usually floating during an ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This intermediate node is used to drive the gate of an upper trigger transistor. A lower trigger transistor has a gate node that is charged by the ESD pulse on the pad through a coupling capacitor. When the coupled ESD pulse turns on the trigger transistors, the trigger transistors turn on a silicon-controlled rectifier (SCR) that is integrated with the trigger transistors.

摘要翻译： 具有非常薄的栅极氧化物的晶体管通过在输出焊盘和接地之间串联两个或更多个晶体管来保护免受氧化物故障。 两个级联晶体管之间的中间源极/漏极节点通常在ESD测试期间浮置，延迟了寄生侧面NPN晶体管的快速恢复导通。 该中间节点用于驱动上触发晶体管的栅极。 下触发晶体管具有通过耦合电容器通过焊盘上的ESD脉冲对其进行充电的栅极节点。 当耦合的ESD脉冲接通触发晶体管时，触发晶体管导通与触发晶体管集成的可控硅整流器（SCR）。

公开(公告)号：US06842059B1

公开(公告)日：2005-01-11

申请号：US10709132

申请日：2004-04-15

申请人： Ke Wu

发明人： Ke Wu

IPC分类号： H03K3/012 ,  H03K3/037 ,  H03K3/12

CPC分类号： H03K3/0372 ,  H03K3/012

摘要： A register chip for double-data-rate (DDR) memory modules operates in 1:1 mode or 1:2 mode. A differential input clock is buffered to generate a slave clock that continuously clocks slave stages of flip-flops, and gated to generate a first clock pulsing only in 1:1 mode and a second clock pulsing only in 1:2 mode. The master stage has two input transmission gates, one activated by the first clock and another activated by the second clock. In 1:1 mode a first data bit is sampled by the first clock, but in 1:2 mode a second data bit is sampled by the second clock. The sampled bit is inverted and applied to the slave stage and to a feedback gate that has transistors gated by the first and second clocks. The clock-to-output delay is improved since an output mux is replaced by the muxing function built into the master stage.

摘要翻译： 用于双数据速率（DDR）存储器模块的寄存器芯片以1：1模式或1：2模式运行。 差分输入时钟被缓冲以产生从时钟，其连续地触发触发器的从动级，并且门控仅产生以1：1模式脉冲的第一时钟脉冲，而第二时钟脉冲仅在1：2模式下脉冲。 主级有两个输入传输门，一个由第一个时钟激活，另一个由第二个时钟激活。 在1：1模式下，第一个数据位由第一个时钟采样，但在1：2模式下，第二个数据位由第二个时钟采样。 采样位被反相并施加到从动级和具有由第一和第二时钟门控的晶体管的反馈门。 时钟到输出延迟得到改善，因为输出多路复用器被内置于主机级的复用功能所代替。

公开(公告)号：US5719427A

公开(公告)日：1998-02-17

申请号：US783626

申请日：1997-01-14

申请人： Paul C. F. Tong ,  Chi-Hung Hui

发明人： Paul C. F. Tong ,  Chi-Hung Hui

IPC分类号： H01L27/02 ,  H01L27/115 ,  H01L23/62

CPC分类号： H01L27/115 ,  H01L27/0255

摘要： A non-volatile memory cell uses a p+ diffusion region spaced a lateral distance from the n+ drain of the n-channel programmable transistor. A diode between this p+ diffusion and the n+ drain has a low breakdown voltage because of the close spacing of the high-doping n+ and p+ diffusions. This diode generates electrons when avalanche breakdown occurs. The avalanche electrons are swept up into the programmable gate during programming. Since the avalanche electrons are generated by the diode rather than by the programmable transistor itself, programming efficiency no longer depends on the channel length and other parameters of the programmable transistor. The breakdown voltage of the diode is adjusted by varying the lateral spacing between the n+ drain and the p+ diffusion. Smaller lateral spacing enter avalanche breakdown at lower voltages and thus program the programmable transistor at a lower drain voltage. A drain voltage less than the power supply is possible with the diode, eliminating the need for a charge pump for the drain. A deep p-type implant under the n+ drain can also form the diode. The diode can be used for input-protection (ESD) devices.

摘要翻译： 非易失性存储单元使用与n沟道可编程晶体管的n +漏极隔开横向距离的p +扩散区域。 由于高掺杂n +和p +扩散的紧密间隔，该p +扩散与n +漏极之间的二极管具有低的击穿电压。 当发生雪崩击穿时，该二极管产生电子。 在编程期间，雪崩电子被扫描到可编程门。 由于雪崩电子由二极管而不是由可编程晶体管本身产生，所以编程效率不再取决于通道长度和可编程晶体管的其他参数。 通过改变n +漏极和p +扩散之间的横向间隔来调节二极管的击穿电压。 较小的横向间隔在较低的电压下进入雪崩击穿，从而将可编程晶体管编程在较低的漏极电压。 通过二极管可以实现小于电源的漏极电压，无需使用漏极的电荷泵。 n +漏极下的深p型注入也可以形成二极管。 二极管可用于输入保护（ESD）器件。

公开(公告)号：US08749285B1

公开(公告)日：2014-06-10

申请号：US13833132

申请日：2013-03-15

申请人： Pericom Semiconductor Corporation

发明人： Kwok Wing Choy

IPC分类号： H03L7/00

CPC分类号： H04L25/03343 ,  H04L25/0272 ,  H04L25/03878 ,  H04N21/43635

摘要： Differential buffers are described that combine aspects of voltage-mode buffers with current injection to achieve the tunability associated with current-mode buffers as well as the low current and low power associated with voltage-mode buffers.

摘要翻译： 描述了将电压模式缓冲器与电流注入相结合的差分缓冲器，以实现与电流模式缓冲器相关的可调谐性以及与电压模式缓冲器相关的低电流和低功率。

公开(公告)号：US20120242377A1

公开(公告)日：2012-09-27

申请号：US13071448

申请日：2011-03-24

申请人： Tony Yeung ,  Michael Y. Zhang

发明人： Tony Yeung ,  Michael Y. Zhang

IPC分类号： H03K3/00

CPC分类号： H03F3/195 ,  H03F3/45183 ,  H03F2200/541 ,  H03F2203/45366 ,  H03F2203/45631 ,  H03F2203/45702 ,  H03F2203/45731 ,  H04L25/0272 ,  H04L25/0286

摘要： A re-driver circuit has pre-driver, intermediate, and output stages. Pre-emphasis on the output is generated by the intermediate stage and injected into an output stage. The intermediate stage is a frequency-tuned amplifier that has an inductive-capacitive L-C tank circuit that is tuned to a desired frequency of the output. The intermediate stage does not directly drive the output stage. Instead, an on-chip coupling transformer couples the L-C tank circuit to the output stage. The coupling transformer has a first inductor that is part of the L-C tank circuit in the intermediate stage, and a second inductor that is part of the output stage. Mutual inductance between the first inductor and the second inductor inductively couple a pre-emphasis voltage onto the output. The magnitude of the pre-emphasis can be changed by adjusting current in the intermediate stage.

摘要翻译： 重新驱动电路具有预驱动器，中间和输出级。 输出的预加重由中间阶段产生并注入输出级。 中间级是调谐放大器，其具有调谐到输出的期望频率的电感 - 电容L-C谐振电路。 中间阶段不直接驱动输出级。 相反，片上耦合变压器将L-C电路耦合到输出级。 耦合变压器具有作为中间级的L-C电路的一部分的第一电感器和作为输出级的一部分的第二电感器。 第一电感和第二电感之间的相互电感将预加重电压感应耦合到输出上。 可以通过调整中间阶段的电流来改变预加重的幅度。

公开(公告)号：US07480303B1

公开(公告)日：2009-01-20

申请号：US10908515

申请日：2005-05-16

申请人： Henry P. Ngai

发明人： Henry P. Ngai

IPC分类号： H04L12/56 ,  H04L12/28

CPC分类号： H04L49/351 ,  H04L49/101 ,  H04L49/103 ,  H04L49/602 ,  H04L49/90 ,  H04L49/901 ,  H04L69/18

摘要： A Pseudo-Ethernet switch has a routing table that uses Ethernet media-access controller (MAC) addresses to route Ethernet packets through a switch fabric between an input port and an output port. However, the input port and output port have Peripheral Component Interconnect Express (PCIE) interfaces that read and write PCI-Express packets to and from host-processor memories. When used in a blade system, host processor boards have PCIE physical links that connect to the PCIE ports on the Pseudo-Ethernet switch. The Pseudo-Ethernet switch does not have Ethernet MAC and Ethernet physical layers, saving considerable hardware. The switch fabric can be a cross-bar switch or can be a shared memory that stores Ethernet packet data embedded in the PCIE packets. Write and read pointers for a buffer storing an Ethernet packet in the shared memory can be passed from input to output port to perform packet switching.

摘要翻译： 伪以太网交换机具有使用以太网媒体访问控制器（MAC）地址通过输入端口和输出端口之间的交换结构路由以太网数据包的路由表。 然而，输入端口和输出端口具有从主机处理器存储器读取和写入PCI-Express数据包的外围组件互连Express（PCIE）接口。 当用于刀片系统时，主处理器板具有连接到伪以太网交换机上的PCIE端口的PCIE物理链路。 伪以太网交换机没有以太网MAC和以太网物理层，节省了大量的硬件。 交换结构可以是交叉开关，也可以是存储嵌入在PCIE数据包中的以太网数据包数据的共享存储器。 用于存储共享存储器中的以太网数据包的缓冲区的写入和读取指针可以从输入到输出端口传递到执行数据包交换。

公开(公告)号：US07464174B1

公开(公告)日：2008-12-09

申请号：US10906783

申请日：2005-03-07

申请人： Henry P. Ngai

发明人： Henry P. Ngai

IPC分类号： G06F15/16 ,  G06F15/173

CPC分类号： H04L12/4625 ,  H04L49/35

摘要： A network connection is transparently shared among two or more processors. A shared network interface controller (NIC) has two or more sets of context registers that may include Ethernet command and pointer registers. Each set of context registers is accessed by a different processor. The processors are separated from the shared NIC by an Advanced Switching (AS) network. AS packets to write the context registers are embedded in AS packets that contain turnpool information that specifies a route through the AS network. Turnpools for AS packets from the different processors are unique and used to indicate which set of context registers to access. Each turnpool-identified context is assigned a different external network (Ethernet) address. External packets received by the shared NIC from the external network are sent inside AS packets over the AS network to the correct processor by associating the packet's external network address with a turnpool-context.

摘要翻译： 网络连接在两个或多个处理器之间透明地共享。 共享网络接口控制器（NIC）具有两组或多组可能包括以太网命令和指针寄存器的上下文寄存器。 每组上下文寄存器由不同的处理器访问。 处理器通过高级交换（AS）网络与共享NIC分离。 AS写入上下文寄存器的数据包嵌入到包含通过AS网络指定路由的交换机信息的AS数据包中。 来自不同处理器的AS数据包的Turnpools是唯一的，用于指示要访问的哪组上下文寄存器。 每个车库识别的上下文都被分配一个不同的外部网络（以太网）地址。 通过将外部网络的共享NIC接收到的外部数据包通过AS网络在AS数据包中通过将数据包的外部网络地址与转换池上下文相关联而发送到正确的处理器。

公开(公告)号：US07107384B1

公开(公告)日：2006-09-12

申请号：US10708412

申请日：2004-03-01

申请人： Baohua Chen ,  Kimchung Arthur Wong ,  Zhinan Zhou

发明人： Baohua Chen ,  Kimchung Arthur Wong ,  Zhinan Zhou

IPC分类号： G06F13/14 ,  G06F13/36 ,  G06K9/34 ,  G06F3/00

CPC分类号： G06F13/4027 ,  G06F12/0862 ,  G06F2212/6022 ,  G06F2213/0024

摘要： A Peripheral Component Interconnect (PCI) bridge between two buses prefetches read data into a cache. The number of cache lines to prefetch is predicted by a prefetch counter. One prefetch counter is kept for each type of memory-read command: basic memory-read (MR), memory-read-line (MRL) that reads a cache line, and memory-read-multiple (MRM) that reads multiple cache lines. For each type of read command, counters are kept of the number of completed commands, bus-disconnects (indicating under-fetch), and master-discard of data (indicating over-fetch). After a predetermined number of execution of each type of command, the command's prefetch counter is incremented if under-fetching occurred, or decremented if over-fetching occurred, as indicated by the disconnect and discard counters for that type of read command. The command's other counters are reset. Prefetching is optimized for each type of read command. MRM can prefetch more data than MRL or MR.

摘要翻译： 两个总线之间的外围组件互连（PCI）桥接预读取数据到高速缓存中。 要预取的高速缓存行数由预取计数器预测。 对于每种类型的存储器读取命令，保留一个预取计数器：读取高速缓存行的基本存储器读取（MR），存储器读取行（MRL）以及读取多个高速缓存行的存储器读取多个（MRM） 。 对于每种类型的读取命令，计数器都保留已完成命令的数量，总线断开（指示欠载）和数据丢弃（表示超出）。 在每种类型的命令执行预定数量的执行之后，如果发生欠牵引，则命令的预取计数器递增，如果发生超速提取则递减，如该类型的读取命令的断开和丢弃计数器所示。 命令的其他计数器复位。 针对每种类型的读取命令优化预取。 MRM可以预取比MRL或MR更多的数据。