公开(公告)号：US06912598B1

公开(公告)日：2005-06-28

申请号：US09627703

申请日：2000-07-28

Applicant: Lorenzo Bedarida ,  Antonino Geraci ,  Mauro Sali ,  Simone Bartoli

Inventor： Lorenzo Bedarida ,  Antonino Geraci ,  Mauro Sali ,  Simone Bartoli

IPC: G11C16/10 ,  G11C16/26 ,  G06F9/28 ,  G06F13/16

CPC classification number: G11C16/10 ,  G11C16/26

Abstract: An electrically alterable semiconductor memory comprises at least two substantially independent memory banks, and a first control circuit for controlling operations of electrical alteration of the content of the memory. The first control circuit permits the selective execution of an operation of electrical alteration of the content of one of the at least two memory banks. The memory also comprises second control circuit that permits, simultaneously with said operation of electrical alteration of the content of one of the at least two memory banks, a burst mode, page mode, or standard read operation for reading the content of the other memory bank.

Abstract translation: 一种电可更改的半导体存储器包括至少两个基本上独立的存储体，以及第一控制电路，用于控制存储器内容的电气改变的操作。 第一控制电路允许选择性地执行对至少两个存储体之一的内容的电气改变的操作。 存储器还包括第二控制电路，其允许同时对所述至少两个存储器组之一的内容进行电气改变的所述操作，用于读取另一个存储体的内容的突发模式，寻呼模式或标准读取操作 。

公开(公告)号：US09917540B2

公开(公告)日：2018-03-13

申请号：US14937248

申请日：2015-11-10

Applicant: STMicroelectronics S.r.l.

Inventor： Michele Boscolo Berto ,  Siro Vittoni

IPC: H02P6/14 ,  H02P6/18 ,  H02P6/182 ,  H02P6/185 ,  H02P6/15 ,  H02K1/34 ,  H02K3/04

CPC classification number: H02P6/182 ,  H02P6/157 ,  H02P6/185

Abstract: A control circuit controls the operation of a brushless DC (BLDC) sensorless motor having a first terminal connected to a first winding, a second terminal connected to a second winding and a third terminal connected to a third winding. A driver circuit applies drive signals to the first and second terminals and places the third terminal in a high-impedance state. The drive signals include first drive signals at a first current amplitude and second drive signals at a second current amplitude different from the first current amplitude. A differencing circuit senses a first mutual inductance voltage at the third terminal in response to the first drive signals and senses a second mutual inductance voltage at the third terminal in response to the second drive signals. The differencing circuit further determines a difference between the first and second mutual inductance voltages and produces a difference signal that is used for zero-crossing detection and rotor position sensing.

公开(公告)号：US08633583B2

公开(公告)日：2014-01-21

申请号：US11879239

申请日：2007-07-16

Applicant: Federico Giovanni Ziglioli ,  Giovanni Graziosi ,  Mark Andrew Shaw ,  Mario Francesco Cortese ,  Conrad Max Cachia

Inventor： Federico Giovanni Ziglioli ,  Giovanni Graziosi ,  Mark Andrew Shaw ,  Mario Francesco Cortese ,  Conrad Max Cachia

IPC: H01L23/04

CPC classification number: B81B7/007 ,  B81B7/0048 ,  B81B2207/096 ,  B81C2203/0154 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device and a package substrate core having an upper and a lower surface. At least one pair of metal layers coats the upper and lower surfaces of the package substrate core. One pair of solder mask layers coats the outer metal layers of the at least one pair of metal layers. A plurality of vias is formed across the package substrate core and the at least one pair of metal layers. Advantageously, the plurality of vias is substantially distributed according to a homogeneous pattern in an area that is to be covered by the damage-sensitive device. A method for the production of such semiconductor package substrate is also described.

Abstract translation: 一种适于支撑损伤敏感器件的半导体封装衬底和具有上表面和下表面的封装衬底芯。 至少一对金属层涂覆封装衬底芯的上表面和下表面。 一对焊接掩模层涂覆至少一对金属层的外金属层。 跨越封装衬底芯和至少一对金属层形成多个通孔。 有利地，多个通孔根据待被损伤敏感装置覆盖的区域中的均匀图案基本上分布。 还描述了制造这种半导体封装基板的方法。

公开(公告)号：US20110001360A1

公开(公告)日：2011-01-06

申请号：US12828736

申请日：2010-07-01

Applicant: Francesco RUA' ,  Salvatore Giuseppe Privitera ,  Tiziana Teresa Signorelli ,  Francesco Pulvirenti

Inventor： Francesco RUA' ,  Salvatore Giuseppe Privitera ,  Tiziana Teresa Signorelli ,  Francesco Pulvirenti

IPC: H02J1/04

CPC classification number: H02J7/35 ,  Y02E10/566 ,  Y02E10/58 ,  Y10T307/593

Abstract: A method of power point tracking for operating a photovoltaic power plant, which includes a DC-DC converter of the output voltage of a panel having a power switch driven by a PWM control signal of variable duty-cycle generated by a PWM control circuit, in discontinuous conduction mode or continuous conduction mode depending on the current load of the converter, is implemented by low cost analog circuits. The method does not require the use of any analog-to-digital conversion, digital processing or storage resources and may use a single voltage sensor.

Abstract translation: 一种用于操作光伏电站的功率点跟踪的方法，其包括具有由PWM控制电路产生的可变占空比的PWM控制信号驱动的功率开关的面板的输出电压的DC-DC转换器， 不连续导通模式或连续导通模式取决于转换器的电流负载，由低成本模拟电路实现。 该方法不需要使用任何模数转换，数字处理或存储资源，并且可以使用单个电压传感器。

公开(公告)号：US20100158108A1

公开(公告)日：2010-06-24

申请号：US12636321

申请日：2009-12-11

Applicant: Megha AGARWAL ,  Sumit JOHAR ,  Kaushik SAHA ,  Emiliano Mario Piccinelli

Inventor： Megha AGARWAL ,  Sumit JOHAR ,  Kaushik SAHA ,  Emiliano Mario Piccinelli

IPC: H04N7/26

CPC classification number: H04N19/48 ,  H04N19/115 ,  H04N19/149 ,  H04N19/152 ,  H04N19/172 ,  H04N19/176 ,  H04N19/18 ,  H04N19/61

Abstract: An embodiment of the present disclosure relates to system comprises an encoding device. Said encoding device comprises a compression unit, a quantizer, a bit estimator, a bit rate encoder and a variable length encoder. An embodiment also is a method of encoding. Said method estimates a number of bits to encode a macroblock after compressing the data stream. Then the estimated bit encoded by a bit rate encoder and further quantized by the quantizer to get the final encoded bit stream. The number of bits required to encode a macroblock is estimated after the quantization process and before the encoding process. The macroblock bit estimator estimates the number of bits required to encode a particular macroblock depending on the quantized AC coefficients of that macroblock and the quantized AC coefficients of the neighboring frames normalized at a macroblock level.

Abstract translation: 本公开的实施例涉及一种包括编码装置的系统。 所述编码装置包括压缩单元，量化器，比特估计器，比特率编码器和可变长度编码器。 实施例也是一种编码方法。 所述方法估计在压缩数据流之后编码宏块的位数。 然后估计比特由比特率编码器编码并由量化器进一步量化以获得最终的编码比特流。 在量化处理之后和编码处理之前估计编码宏块所需的位数。 宏块比特估计器根据该宏块的量化AC系数和在宏块级标准化的相邻帧的量化AC系数来估计对特定宏块进行编码所需的比特数。