公开(公告)号：US20150030058A9

公开(公告)日：2015-01-29

申请号：US11759221

申请日：2007-06-06

Applicant: Badri Varadarajan ,  Eko N. Onggosanusi

Inventor： Badri Varadarajan ,  Eko N. Onggosanusi

IPC: H04B1/38 ,  H04B7/216

CPC classification number: H04B7/0417 ,  H04B7/063 ,  H04B7/0632 ,  H04B7/0634 ,  H04B7/0639 ,  H04L1/0618 ,  H04L25/03929 ,  H04L25/03949

Abstract: The present disclosure provides a receiver, a transmitter and methods of operating a receiver and a transmitter. In one embodiment, the receiver includes a receive portion employing transmission signals from a transmitter, having multiple transmit antennas, that is capable of transmitting at least one spatial codeword and adapting a transmission rank. The receiver also includes a feedback generator portion configured to provide a channel quality indicator that is feedback to the transmitter, wherein the channel quality indicator corresponds to at least one transmission rank.

Abstract translation: 本公开提供了一种接收机，发射机以及操作接收机和发射机的方法。 在一个实施例中，接收机包括采用来自具有多个发射天线的发射机的传输信号的接收部分，其能够传送至少一个空间码字并适配传输秩。 接收机还包括反馈发生器部分，其被配置为提供对发射机的反馈的信道质量指示符，其中信道质量指示符对应于至少一个传输等级。

公开(公告)号：US08309438B2

公开(公告)日：2012-11-13

申请号：US12706116

申请日：2010-02-16

Applicant: Luigi Colombo ,  Robert M. Wallace ,  Rodney S. Ruoff

Inventor： Luigi Colombo ,  Robert M. Wallace ,  Rodney S. Ruoff

IPC: H01L21/20

CPC classification number: H01L21/02612 ,  H01L21/02527

Abstract: A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.

Abstract translation: 一种使用碳的离子注入合成石墨烯的方法和半导体器件。 使用离子注入将碳注入金属中。 在碳分布在金属中之后，对金属进行退火和冷却，以便从金属沉淀碳以在金属表面上形成一层石墨烯。 然后将金属/石墨烯表面转移到电介质层，使得石墨烯层被放置在电介质层的顶部上。 然后去除金属层。 或者，凹陷区域被图案化并蚀刻在位于基底上的电介质层中。 金属后来形成在这些凹陷区域。 然后使用离子注入将碳注入到金属中。 然后可以对金属进行退火和冷却，以便从金属沉淀碳以在金属表面上形成一层石墨烯。

公开(公告)号：US20100253840A1

公开(公告)日：2010-10-07

申请号：US12418712

申请日：2009-04-06

Applicant: JAMES E. NAVE

Inventor： JAMES E. NAVE

IPC: H04N5/04 ,  H04N7/12 ,  H04N5/66

CPC classification number: H04N9/642 ,  G09G5/003 ,  G09G5/005 ,  G09G2370/047 ,  G09G2370/12

Abstract: A method for automatic format detection, video decoder and video display devices therefrom. A video input having an algorithm-based first graphics format is received that carries an RGB video signal, Hsync signal and a Vsync signal. From the Hsync signal and Vsync signal, a plurality of different measured timing parameters are generated including a total number of vertical lines per frame, a total number of vertical lines per pulse width of the Vsync signal, a total number of reference clock cycles per vertical line, and measured polarity information for the Vsync and Hsync signal. An algorithm automatically generates a format detection result that represents the first graphics format using the plurality of different measured timing parameters and the measured polarity information, including a plurality of horizontal and vertical timing information for configuring a video display for the algorithm-based first graphics format.

Abstract translation: 一种用于自动格式检测，视频解码器和视频显示设备的方法。 接收具有基于算法的第一图形格式的视频输入，其携带RGB视频信号，Hsync信号和Vsync信号。 根据Hsync信号和Vsync信号，产生多个不同的测量定时参数，包括每帧垂直线的总数，Vsync信号的每个脉冲宽度的垂直线总数，每垂直的参考时钟周期的总数 线和测量的Vsync和Hsync信号的极性信息。 算法自动生成使用多个不同的测量定时参数和测量的极性信息来表示第一图形格式的格式检测结果，包括用于配置用于基于算法的第一图形格式的视频显示的多个水平和垂直定时信息 。

公开(公告)号：US20100079132A1

公开(公告)日：2010-04-01

申请号：US12286627

申请日：2008-10-01

Applicant: Gerald W. Steele ,  Edward Mullins

Inventor： Gerald W. Steele ,  Edward Mullins

IPC: G01R1/30

CPC classification number: G01R1/30 ,  G01R1/203

Abstract: An integrated circuit current shunt amplifier (2A) includes an amplifier (9) having a (+) input connected to a first terminal (5A) of a shunt resistor (RSHUNT). An output transistor (24) has a gate coupled to an output of the amplifier, a source coupled to a (−) input of the amplifier, and a drain coupled to a first terminal of an output resistor (ROUT). A gain resistor (RGAIN) is coupled between the (−) input of the amplifier and a second terminal of the shunt resistor. The gain resistor has a temperature coefficient which is essentially the same as that of the shunt resistor.A voltage regulator (26) can be coupled between the second terminal of the shunt resistor and a low-side supply voltage terminal (27) of the amplifier. A charge pump (30) can provide a below-ground voltage on a second terminal of the output resistor. A difference amplifier (31) coupled to the drain and referenced to the below-ground voltage produces an output voltage (Vout) referenced to ground.

Abstract translation: 集成电路电流分流放大器（2A）包括具有连接到分流电阻器（RSHUNT）的第一端子（5A）的（+）输入的放大器（9）。 输出晶体管（24）具有耦合到放大器的输出的栅极，耦合到放大器的（ - ）输入的源极和耦合到输出电阻器（ROUT）的第一端子的漏极。 增益电阻（RGAIN）耦合在放大器的（ - ）输入端和分流电阻的第二端之间。 增益电阻的温度系数基本上与分流电阻的温度系数相同。 电压调节器（26）可以耦合在分流电阻器的第二端子和放大器的低侧电源电压端子（27）之间。 电荷泵（30）可以在输出电阻器的第二端上提供地下电压。 耦合到漏极并参考地下电压的差分放大器（31）产生参考地的输出电压（Vout）。

公开(公告)号：US20090278238A1

公开(公告)日：2009-11-12

申请号：US12463282

申请日：2009-05-08

Applicant: THOMAS D. BONIFIELD ,  BRIAN E. GOODLIN ,  MONA M. EISSA

Inventor： THOMAS D. BONIFIELD ,  BRIAN E. GOODLIN ,  MONA M. EISSA

IPC: H01L23/52 ,  H01L21/306 ,  H01L21/304

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.

Abstract translation: 一种用于制造IC的方法，包括从第一至第
一通孔（TSV）和IC及其电子组件。 提供具有包括顶部半导体表面和底部表面的衬底厚度的衬底，其包括至少一个嵌入式TSV，其包括形成在电介质衬垫上的介电衬垫和导电填充材料。 基板的底表面的一部分被机械地移除以接近但不到达嵌入的TSV尖端。 在机械去除之后，具有保护层厚度的保护基层保留在嵌入TSV的尖端上。 用于去除保护基底层的机械蚀刻除外的化学蚀刻用于形成整体的TSV尖端，其具有通常从基底的底表面突出的暴露尖端部分。 化学蚀刻通常是三步化学蚀刻。

公开(公告)号：US20090224795A1

公开(公告)日：2009-09-10

申请号：US12209986

申请日：2008-09-12

Applicant: Paul Edward Nicollian ,  Anand T. Krishnan ,  Vijay K. Reddy

Inventor： Paul Edward Nicollian ,  Anand T. Krishnan ,  Vijay K. Reddy

IPC: G01R31/26

CPC classification number: G01R31/2884 ,  G01R31/2648 ,  G01R31/2858 ,  H01L22/34

Abstract: A method for evaluating gate dielectrics (100) includes providing a test structure (101). The test structure includes a gate stack that includes a gate electrode on a gate dielectric on a substrate, and at least one diffusion region diffused in the substrate including a portion below the gate stack and a portion beyond the gate stack. Pre-stress off-state I-V testing (102) is performed on the test structure to obtain pre-stress I-V test data, wherein the pre-stress off-state I-V testing includes a first measurement involving the gate electrode, the substrate and the diffusion region, a second measurement involving the gate electrode and the substrate with the diffusion region floating, and a third measurement involving the gate electrode and the diffusion region with the substrate floating. The test structure is then stressed (103) including electrically stressing for a time (t). Following the stressing, post-stress I-V testing is performed (104) wherein the first, second and third measurements are repeated to obtain post-stress I-V test data. The gate dielectric is evaluated (105) from the pre-stress and post-stress I-V test data.

Abstract translation: 一种用于评估栅极电介质（100）的方法包括提供测试结构（101）。 测试结构包括栅极堆叠，其包括在衬底上的栅极电介质上的栅极电极，以及扩散在衬底中的至少一个扩散区域，其包括栅极堆叠下方的部分和超过栅极堆叠的部分。 在测试结构上执行预应力关闭状态IV测试（102）以获得预应力IV测试数据，其中预应力off-state IV测试包括涉及栅电极，衬底和扩散的第一测量 区域，涉及所述栅电极和所述扩散区域的衬底浮动的第二测量，以及涉及所述栅电极和所述扩散区域的第三测量，所述衬底浮置。 然后将测试结构应力（103）包括电应力一段时间（t）。 在应力之后，执行后应力I-V测试（104），其中重复第一，第二和第三测量以获得后应力I-V测试数据。 从预应力和后应力I-V测试数据评估栅极电介质（105）。

公开(公告)号：US20090188524A1

公开(公告)日：2009-07-30

申请号：US12022924

申请日：2008-01-30

Applicant: Jason J. New ,  Antonio Ibarra-Rivera ,  Joe M. Bockemehl, JR.

Inventor： Jason J. New ,  Antonio Ibarra-Rivera ,  Joe M. Bockemehl, JR.

IPC: B08B6/00

CPC classification number: B08B7/0035 ,  C23C16/4405 ,  C30B25/14 ,  H01J37/3244 ,  H01J37/32834 ,  H01J37/32862

Abstract: An automatic method (100) of in-situ cleaning a processing system (211) including a process chamber (213) pumped by a roughing pump (219) and a turbomolecular pump (217) includes the steps of automatically performing a first RF plasma clean (110) (referred to herein as a chamber clean) to clean the process chamber, wherein the turbomolecular pump (217) is isolated and the roughing pump (219) pumps the processing chamber (213). The turbomolecular pump (217) is automatically switched on to pump the processing chamber (213). While the turbomolecular pump is pumping the processing chamber (213), a second RF plasma clean (115) (referred to herein as an automatic turbo clean) is performed clean the turbomolecular pump (217). In embodiments of the invention the turbo clean (115) automatically sets at least one gas flow, an RF power, and a pressure in the chamber (213).

Abstract translation: 一种处理系统（211）的自动方法（100），包括由粗抽泵（219）和涡轮分子泵（217）泵送的处理室（213），包括以下步骤：自动执行第一RF等离子体清洁 （110）（在本文中称为室清洁）以清洁处理室，其中分离的涡轮分子泵（217）被隔离，粗加工泵（219）泵送处理室（213）。 涡轮分子泵（217）自动打开以泵送处理室（213）。 当涡轮分子泵泵送处理室（213）时，执行第二射频等离子体清洁（115）（这里称为自动涡轮清洁）清洁涡轮分子泵（217）。 在本发明的实施例中，涡轮清洁器（115）自动设定腔室（213）中的至少一个气流，RF功率和压力。

公开(公告)号：US20090161410A1

公开(公告)日：2009-06-25

申请号：US11962713

申请日：2007-12-21

Applicant: Theodore W. Houston

Inventor： Theodore W. Houston

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C11/412

Abstract: The present disclosure provides a seven transistor static random access memory (7T SRAM) cell. In one embodiment, the 7T SRAM cell includes a pair of cross-coupled inverters configured to provide a memory element having first and second storage nodes. The 7T SRAM cell also includes a Read isolation transistor having a control element connected to one of the storage nodes of the cross-coupled transistor inverters and configured to provide a buffered Read output. The 7T SRAM cell further includes a Read pass gate transistor controlled by a Read word line and connected between the Read isolation transistor and a read bit line. Additionally, the 7T SRAM cell still further includes a Write pass gate transistor controlled by a Write word line and connected between one of the storage nodes of the cross-coupled inverters and a Write bit line to write either state of the memory element.

Abstract translation: 本公开提供了七个晶体管静态随机存取存储器（7T SRAM）单元。 在一个实施例中，7T SRAM单元包括一对交叉耦合的反相器，被配置为提供具有第一和第二存储节点的存储元件。 7T SRAM单元还包括读隔离晶体管，其具有连接到交叉耦合晶体管反相器的存储节点之一的控制元件，并且被配置为提供缓冲的读输出。 7T SRAM单元还包括一个由读取字线控制并连接在读取隔离晶体管和读取位线之间的读通道晶体管晶体管。 此外，7T SRAM单元还包括由写入字线控制并连接在交叉耦合反相器的一个存储节点之间的写入通道栅极晶体管和写入位线，以写入存储器元件的任一状态。

公开(公告)号：US20090057889A1

公开(公告)日：2009-03-05

申请号：US12048294

申请日：2008-03-14

Applicant: Rajen M. Murugan ,  Robert F. McCarthy ,  Baher S. Haroun ,  Peter R. Harper

Inventor： Rajen M. Murugan ,  Robert F. McCarthy ,  Baher S. Haroun ,  Peter R. Harper

IPC: H01L23/48 ,  H01L21/20 ,  H01L21/44

CPC classification number: H01L23/3114 ,  H01L23/5223 ,  H01L23/525 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19104

Abstract: One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts.

Abstract translation: 本发明的一个方面提供一种包括具有最外表面的微芯片的半导体器件。 第一和第二接合焊盘位于微芯片上并且在最外表面附近。 第一UBM触点位于最外表面和第一和第二接合焊盘之间。 第一个UBM触点与第一个焊盘相抵消。 第二UBM触点位于最外表面上以及第一和第二接合焊盘之间。 第二UBM触点偏离第二接合焊盘，并且由微芯片支撑的电容器位于第一和第二UBM触点之间。

公开(公告)号：US20080291185A1

公开(公告)日：2008-11-27

申请号：US11754176

申请日：2007-05-25

Applicant: Hector C. Rodriguez ,  James N. Hall

Inventor： Hector C. Rodriguez ,  James N. Hall

IPC: G09G3/00

CPC classification number: G09G3/34

Abstract: In accordance with the teachings of the present disclosure, a method and system for controlling spatial light modulator buses are provided. In accordance with one embodiment of the present disclosure, a bus controller includes a configurable bus interface having first and second modes of operation. The first mode of operation is configured to interface with a single spatial light modulator. The second mode of operation is configured to interface in parallel with a plurality of spatial light modulators. In accordance with another embodiment of the present disclosure, a method of controlling a bus includes configuring a bus interface of a bus controller to interface in parallel with a plurality of digital micromirror devices.

Abstract translation: 根据本公开的教导，提供了一种用于控制空间光调制器总线的方法和系统。 根据本公开的一个实施例，总线控制器包括具有第一和第二操作模式的可配置总线接口。 第一操作模式被配置为与单个空间光调制器接口。 第二操作模式被配置为与多个空间光调制器并联接口。 根据本公开的另一实施例，一种控制总线的方法包括配置总线控制器的总线接口以与多个数字微镜器件并联接口。