公开(公告)号：US11687457B2

公开(公告)日：2023-06-27

申请号：US17460439

申请日：2021-08-30

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria

IPC分类号： G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F12/0808 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0895 ,  G06F12/0831

CPC分类号： G06F12/0811 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/3867 ,  G06F9/467 ,  G06F9/544 ,  G06F9/546 ,  G06F11/3037 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/1668 ,  G06F2212/1021 ,  G06F2212/608

摘要： A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.

公开(公告)号：US09575122B2

公开(公告)日：2017-02-21

申请号：US15259619

申请日：2016-09-08

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Lee D. Whetsel

IPC分类号： G01R31/3177 ,  G01R31/3185

CPC分类号： G01R31/3177 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/318536 ,  G01R31/318544

摘要： The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.

摘要翻译： 本公开描述了一种用于允许从被测电路的扫描输出输出的响应数据被格式化并作为输入到被测电路的扫描输入的刺激数据的新的方法和装置。 此外，本公开描述了一种用于允许从被测电路的扫描输出输出的响应数据被格式化并用作预期数据以与从被测电路输出的响应数据进行比较的新颖方法和装置。 在本公开中还提供和描述了另外的实施例。

公开(公告)号：US09350574B2

公开(公告)日：2016-05-24

申请号：US14183211

申请日：2014-02-18

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Huawen Jin ,  Jawaid Ahmad ,  Yaqi Hu

IPC分类号： H03H7/30 ,  H04L25/03 ,  H04L25/02

CPC分类号： H04L25/03885 ,  H04L25/0272 ,  H04L25/0286 ,  H04L25/03343 ,  H04L25/03834

摘要： An apparatus comprises a differential equalizer having: a) a first differential input, b) a second differential input, c) a first differential output, and d) a second differential output; a frequency detector coupled to the first and second differential inputs; an amplifier coupled to a first differential output and a second differential output of the differential equalizer; and a logical combiner having a first input coupled to an output of the frequency detector and an output coupled to a control input of the amplifier, wherein the logical combiner can mask at least one received de-emphasis parameter.

摘要翻译： 一种装置包括差分均衡器，其具有：a）第一差分输入，b）第二差分输入，c）第一差分输出，以及d）第二差分输出; 耦合到所述第一和第二差分输入的频率检测器; 耦合到所述差分均衡器的第一差分输出和第二差分输出的放大器; 以及逻辑组合器，其具有耦合到所述频率检测器的输出的第一输入和耦合到所述放大器的控制输入的输出，其中所述逻辑组合器可以屏蔽至少一个所接收的去加重参数。

公开(公告)号：US20090256856A1

公开(公告)日：2009-10-15

申请号：US12100818

申请日：2008-04-10

申请人： Erin Patricia Murphy Smoyer ,  Gregory S. Pettitt ,  Jason Ryan Thompson

发明人： Erin Patricia Murphy Smoyer ,  Gregory S. Pettitt ,  Jason Ryan Thompson

IPC分类号： G09G5/02

CPC分类号： G09G5/02 ,  G09G2320/0673 ,  G09G2340/06

摘要： In accordance with one embodiment, a method for emulating the color performance of a display system includes determining an expected first color gamut of the display system. Display data is converted into a format that emulates the first color gamut. The converted display data is displayed by a different display system having an expected second color gamut different than the expected first color gamut.

摘要翻译： 根据一个实施例，用于模拟显示系统的颜色性能的方法包括确定显示系统的期望的第一色域。 显示数据被转换成模拟第一个色域的格式。 经转换的显示数据由具有与期望的第一色域不同的期望的第二色域的不同显示系统显示。

公开(公告)号：US5844426A

公开(公告)日：1998-12-01

申请号：US665144

申请日：1996-06-13

申请人： Benjamin Joseph Sheahan ,  Richard Charles Pierson

发明人： Benjamin Joseph Sheahan ,  Richard Charles Pierson

IPC分类号： G11B20/14 ,  H03K19/0185 ,  H03K19/0175 ,  H03K19/082 ,  H03K19/094

CPC分类号： H03K19/018528 ,  G11B20/1403

摘要： A level shift is provided between a first level and a second level for a first and second compensatory signal. Power supply variations are measured and the levels are compensated for these power supply variations so that the power supply does not affect the first and second levels.

摘要翻译： 在第一和第二补偿信号的第一电平和第二电平之间提供电平移位。 测量电源变化，并且为这些电源变化补偿电平，使得电源不影响第一和第二电平。

公开(公告)号：US5407842A

公开(公告)日：1995-04-18

申请号：US255502

申请日：1994-06-08

申请人： Francis J. Morris ,  Jau-Yuann Yang ,  Donald L. Plumton ,  Han-Tzong Yuan

发明人： Francis J. Morris ,  Jau-Yuann Yang ,  Donald L. Plumton ,  Han-Tzong Yuan

IPC分类号： H01L21/331 ,  H01L27/06 ,  H01L29/737 ,  H01L21/265

CPC分类号： H01L29/66318 ,  H01L27/0605 ,  H01L29/7371 ,  Y10S148/01 ,  Y10S148/072

摘要： This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.

摘要翻译： 这是一种形成双极晶体管的方法，包括：在衬底上形成具有掺杂类型和掺杂水平的子集电极层; 在子集电极层上形成与子集电极层相同的掺杂类型和较低掺杂水平的第一层; 增加第一层的第一和第二区域的掺杂水平; 在第一层上形成与子集电极层相同的掺杂类型和较低掺杂水平的第二层; 增加在第一层的第一区域之上的第二层的第一区域的掺杂水平，由此子集电极层，第一层的第一区域和第二层的第一区域是晶体管的集电极; 在与所述子集电极层相反的掺杂类型的第二层上形成基底层; 并且在基底层上形成与子集电极层相同的掺杂类型的发射极层。 还公开了其它装置和方法。

公开(公告)号：US10659078B2

公开(公告)日：2020-05-19

申请号：US16200061

申请日：2018-11-26

申请人： Texas Instruments Incorporated

发明人： Jasbir Singh Nayyar ,  Brian Ginsburg ,  Karthik Subburaj

IPC分类号： H04L7/00 ,  H03M13/00 ,  H04J3/06 ,  G01S7/02 ,  G01S13/34 ,  G01S13/87

摘要： A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware clock control that provides a clock signal based on a selected one of the frame pulse and the synchronization signal provided from one of the root timer and another IC chip. The IC chip can further include a plurality of analog to digital converters (ADCs). Each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.

公开(公告)号：US09224592B2

公开(公告)日：2015-12-29

申请号：US14473768

申请日：2014-08-29

申请人： Texas Instruments Incorporated

发明人： John Christopher Shriner ,  Abbas Ali

IPC分类号： H01L21/20 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/115 ,  H01L49/02 ,  H01L21/311 ,  H01J37/32 ,  H01L21/66

CPC分类号： H01L21/02197 ,  H01J37/32963 ,  H01J2237/334 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32139 ,  H01L22/26 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

摘要： A method of etching a ferroelectric capacitor stack structure including conductive upper and lower plates with a ferroelectric material, such as lead-zirconium-titanate (PZT), therebetween, with each of these layers defined by the same hard mask element. The stack etch process involves a plasma etch with a fluorine-bearing species as an active species in the etch of the conductive plates, and a non-fluorine-bearing chemistry for etching the PZT ferroelectric material. An example of the fluorine-bearing species is CF4. Endpoint detection can be used to detect the point at which the upper plate etch reaches the PZT, at which point the gases in the chamber are purged to avoid etching the PZT material with fluorine. A steeper sidewall angle for the capacitor structure can be obtained.

摘要翻译： 一种用诸如钛酸锆（PZT）之类的铁电材料的导电上板和下板蚀刻铁电电容器堆叠结构的方法，其中每个层由同一硬掩模元件限定。 堆叠蚀刻工艺包括在导电板的蚀刻中具有含氟物质作为活性物质的等离子体蚀刻和用于蚀刻PZT铁电材料的非含氟化学物质。 含氟物质的实例是CF 4。 可以使用端点检测来检测上板蚀刻到达PZT的点，此时，腔中的气体被清除以避免用氟蚀刻PZT材料。 可以获得电容器结构的更陡的侧壁角。

公开(公告)号：US08607088B2

公开(公告)日：2013-12-10

申请号：US13226058

申请日：2011-09-06

申请人： Gary L. Swoboda

发明人： Gary L. Swoboda

IPC分类号： G06F1/04

CPC分类号： G01R31/3177 ,  G01R31/317 ,  G06F1/12 ,  G06F1/3206 ,  G06F11/221 ,  G06F11/2284 ,  G06F11/267 ,  H04L7/046

摘要： A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

摘要翻译： 一种方法包括一种系统，该系统包括耦合到根据主机设备和所有远程设备在系统操作期间跟随的状态图主动操作的第一远程设备的主机设备。 该方法还包括在主机设备和第一远程设备根据状态图主动操作时加电第二远程设备。 第二个远程设备确定是初始化为标准协议还是高级协议。 当确定初始化为高级协议时，第二远程设备然后等待同步点序列。

公开(公告)号：US20130032892A1

公开(公告)日：2013-02-07

申请号：US13567552

申请日：2012-08-06

申请人： Hiroshi YASUDA ,  Berthold STAUFER

发明人： Hiroshi YASUDA ,  Berthold STAUFER

IPC分类号： H01L27/06 ,  H01L21/8249

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7833

摘要： A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.

摘要翻译： 通过使用非选择性外延工艺形成双极型晶体管的基极层，使得基极层在集电极有源区域上具有单一结晶区域和多晶硅层，形成包含双极晶体管和MOS晶体管的集成电路的工艺 区域，并且同时注入基极层的MOS栅极层和多晶区域，使得基极 - 集电极结延伸到小于场氧化物深度的三分之一的衬底中，并且垂直累积掺杂 基极层的多晶区域的密度在MOS栅极的垂直累积掺杂密度的80％至125％之间。 包含双极晶体管和通过所描述的工艺形成的MOS晶体管的集成电路。