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公开(公告)号：US20230375920A1
公开(公告)日：2023-11-23
申请号：US18230062
申请日：2023-08-03
发明人： Ming-Hui WENG , Chen-Yu LIU , Chih-Cheng LIU , Yi-Chen KUO , Jia-Lin WEI , Yen-Yu CHEN , Jr-Hung LI , Yahru CHENG , Chi-Ming YANG , Tze-Liang LEE , Ching-Yu CHANG
IPC分类号： G03F7/004 , H01L21/033 , G03F7/00
CPC分类号： G03F7/004 , H01L21/0332 , G03F7/0035
摘要： A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
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公开(公告)号：US20220262701A1
公开(公告)日：2022-08-18
申请号：US17219913
申请日：2021-04-01
发明人： Jia-Liang CHEN , Chi-Ming YANG , Yen-Chao LIN
IPC分类号： H01L23/367 , H01L21/48 , H01L23/31 , H01L21/56 , H01L23/00 , H01L23/373
摘要： A semiconductor packaging device includes a wiring board, a working chip, a heat-dissipating metal lid and a silicon thermal conductivity element. The working chip is mounted on the wiring board, and in-built with an working circuit therein. The silicon thermal conductivity element is thermally coupled to the working chip and the heat-dissipating metal lid, and is electrically isolated from the working circuit and the wiring board.
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公开(公告)号：US20240213112A1
公开(公告)日：2024-06-27
申请号：US18169212
申请日：2023-02-15
发明人： Sheng-Fan YANG , Yen-Chao LIN , Chi-Ming YANG
IPC分类号： H01L23/367 , H01L23/00 , H01L23/31 , H01L25/065
CPC分类号： H01L23/3675 , H01L23/3185 , H01L24/16 , H01L24/32 , H01L25/0655 , H01L24/29 , H01L24/33 , H01L24/73 , H01L24/83 , H01L2224/16227 , H01L2224/2919 , H01L2224/32225 , H01L2224/32257 , H01L2224/32258 , H01L2224/33181 , H01L2224/33505 , H01L2224/73204 , H01L2224/73253 , H01L2224/83192 , H01L2224/83385 , H01L2924/0665 , H01L2924/1616 , H01L2924/16235 , H01L2924/18161
摘要： A semiconductor packaging device includes a packaging module, a heat dissipation cover and a thermal interface material layer. The package module includes a substrate, and a working chip mounted on the substrate. The heat dissipation cover includes a metal cover fixed on the substrate and covering the working chip, an accommodating recess located on the metal cover to accommodate the working chip, and a plurality of protrusive columns respectively formed on the metal cover and distributed within the accommodating recess at intervals. The depth of the accommodating recess is greater than the height of each protrusive column, and the accommodating recess is greater than the working chip. The thermal interface material layer is non-solid, and located within the accommodating recess between the protrusive columns to wrap the protrusive columns and contact with the working chip, the metal cover and the protrusive columns.
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公开(公告)号：US20230402321A1
公开(公告)日：2023-12-14
申请号：US18447539
申请日：2023-08-10
发明人： Po-Hsien CHENG , Chi-Ming YANG , Tze-Liang LEE
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76846 , H01L23/53238 , H01L23/53209 , H01L21/76844 , H01L21/7685 , H01L23/53266 , H01L23/5226
摘要： A layer of carbon (e.g., graphite or graphene) at a metal interface (e.g., between an MEOL interconnect and a gate contact or a source or drain region contact, between an MEOL contact plug and a BEOL metallization layer, and/or between BEOL conductive structures) is used to reduce contact resistance at the metal interface, which increases electrical performance of an electronic device. Additionally, in some implementations, the layer of carbon may help prevent heat transfer from a second metal to a first metal when the second metal is deposited over the first metal. This results in more symmetric deposition of the second metal, which reduces surface roughness and contact resistance at the metal interface. As an alternative, in some implementations, the layer of carbon is etched before deposition of the second metal in order to reduce contact resistance at the metal interface.
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公开(公告)号：US20220367313A1
公开(公告)日：2022-11-17
申请号：US17815950
申请日：2022-07-29
发明人： Jia-Liang CHEN , Chi-Ming YANG , Yen-Chao LIN
IPC分类号： H01L23/367 , H01L21/48 , H01L23/31 , H01L21/56 , H01L23/00 , H01L23/373
摘要： A manufacturing method of a semiconductor packaging device is provided, and the manufacturing method includes steps as follows. A working chip is soldered on one surface of a wiring board so that an working circuit inbuilt inside a chip body of the working chip is electrically connected to the wiring board. A silicon thermal conductivity element is soldered on one surface of a heat-dissipating metal lid. The heat-dissipating metal lid is fixedly covered on the wiring board such that the silicon thermal conductivity element is sandwiched between the chip body and the heat-dissipating metal lid, and the silicon thermal conductivity element is electrically isolated from the working circuit of the chip body and the wiring board.
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6.发明公开公开(公告)号：US20240355623A1
公开(公告)日：2024-10-24
申请号：US18761585
申请日：2024-07-02
发明人： Yi-Chen KUO , Chih-Cheng LIU , Ming-Hui WENG , Jia-Lin WEI , Yen-Yu CHEN , Jr-Hung LI , Yahru CHENG , Chi-Ming YANG , Tze-Liang LEE , Ching-Yu CHANG
IPC分类号： H01L21/027 , H01L21/02
CPC分类号： H01L21/0275 , H01L21/0228 , H01L21/02362
摘要： A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
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7.发明申请MULTI-POINT CHEMICAL MECHANICAL POLISHING END POINT DETECTION SYSTEM AND METHOD OF USING 审中-公开多点化学机械抛光端点检测系统及其使用方法公开(公告)号：US20140148008A1
公开(公告)日：2014-05-29
申请号：US13687492
申请日：2012-11-28
发明人： Jiann Lih WU , Jeng-Jyi HWANG , Soon-Kang HUANG , Chi-Ming YANG
IPC分类号： H01L21/306
CPC分类号： H01L22/12 , B24B37/013 , B24B37/04 , B24B49/12 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： A wafer polishing system including a platen configured to rotate in a first direction, and a polishing head configured to hold a wafer, the polishing head configured to rotate in a second direction. The wafer polishing system further includes an optical sensing system configured to detect a thickness of the wafer at a first location on the platen and a second location on the platen. A first distance from a center of the platen to the first location is different than a second distance from the center of the platen to the second location.
摘要翻译： 一种晶片抛光系统，包括被配置成在第一方向上旋转的压板和被配置为保持晶片的抛光头，所述抛光头构造成沿第二方向旋转。 晶片抛光系统还包括光学感测系统，其被配置为在压板上的第一位置处检测晶片的厚度，并且在压板上检测第二位置。 从压盘的中心到第一位置的第一距离不同于从压板的中心到第二位置的第二距离。
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公开(公告)号：US20130270617A1
公开(公告)日：2013-10-17
申请号：US13915184
申请日：2013-06-11
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , C23C14/022 , C23C14/046 , C23C14/18 , C23C14/221 , C23C16/0263 , C23C16/045 , C23C16/06 , C23C16/48 , C23C16/484 , H01L21/28079 , H01L21/28088 , H01L21/2855 , H01L21/28556 , H01L21/76843 , H01L21/76856 , H01L21/76862 , H01L21/76865 , H01L21/76877 , H01L29/4966 , H01L29/66545
摘要： A gate structure including a substrate and a gate dielectric layer formed over the substrate. The gate structure further includes a workfunction layer over the gate dielectric layer and spacers enclosing the gate dielectric layer and the workfunction layer. A top surface of a portion of the workfunction layer in contact with sidewalls of the spacer is a same distance from the gate dielectric layer as a top surface of a center portion of the work function layer.
摘要翻译： 一种栅极结构，包括在基板上形成的基板和栅极电介质层。 栅极结构还包括在栅极电介质层上的功函数层和包围栅极介电层和功函数层的间隔物。 与间隔物的侧壁接触的功函数层的一部分的顶表面与作为功函数层的中心部分的顶表面的栅介电层相同。
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公开(公告)号：US20230072538A1
公开(公告)日：2023-03-09
申请号：US17971552
申请日：2022-10-22
发明人： Chih-Cheng LIU , Ming-Hui WENG , Jr-Hung LI , Yahru CHENG , Chi-Ming YANG , Tze-Liang LEE , Ching-Yu CHANG
IPC分类号： G03F7/004 , G03F7/38 , G03F7/16 , G03F7/20 , H01L21/027 , C23C16/455 , C23C16/56
摘要： A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. A first precursor and a second precursor are combined. The first precursor is an organometallic having a formula: MaRbXc, where M is one or more of Sn, Bi, Sb, In, and Te, R is one or more of a C7-C11 aralkyl group, a C3-C10 cycloalkyl group, a C2-C10 alkoxy group, and a C2-C10 alkylamino group, X is one or more of a halogen, a sulfonate group, and an alkylamino group, and 1≤a≤2, b≥1, c≥1, and b+c≤4, and the second precursor is one or more of water, an amine, a borane, and a phosphine. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer to the selectively exposed photoresist layer.
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公开(公告)号：US20160136776A1
公开(公告)日：2016-05-19
申请号：US15003258
申请日：2016-01-21
发明人： Bo-I LEE , Soon Kang HUANG , Chi-Ming YANG , Chin-Hsiang LIN
IPC分类号： B24B37/20
CPC分类号： B24B37/20 , B24B53/017
摘要： A method of planarizing a wafer includes pressing the wafer against a planarization pad. The method further includes moving the planarization pad relative to the wafer. The method further includes conditioning the planarization pad using a pad conditioner. Conditioning the planarization pad includes moving the planarization pad relative to the pad conditioner. The pad conditioner includes abrasive particles having aligned tips a substantially constant distance from a surface of substrate of the pad conditioner.
摘要翻译： 平面化晶片的方法包括将晶片压在平坦化焊盘上。 该方法还包括相对于晶片移动平坦化焊盘。 该方法还包括使用垫调节器来调节平坦化垫。 调整平坦化焊盘包括相对于衬垫调节器移动平坦化衬垫。 衬垫调节器包括具有与衬垫调节器的衬底的表面基本恒定距离的对准尖端的磨料颗粒。
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