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1.发明授权Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same 有权具有具有多个垂直嵌入的裸片的基板的多芯片封装及其形成工艺公开(公告)号：US08736065B2
公开(公告)日：2014-05-27
申请号：US12976903
申请日：2010-12-22
IPC分类号： H01L23/00
CPC分类号： H01L25/50 , H01L21/568 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/95 , H01L2224/12105 , H01L2224/19 , H01L2224/221 , H01L2224/2402 , H01L2224/24105 , H01L2224/24137 , H01L2224/24147 , H01L2224/245 , H01L2224/251 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/82005 , H01L2224/82039 , H01L2224/82101 , H01L2224/92244 , H01L2224/95 , H01L2224/95001 , H01L2924/00013 , H01L2924/01006 , H01L2924/01029 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1815 , H01L2924/18162 , H01L2224/82 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first die and a second die wherein the first die and second die are embedded within the substrate such that the second die is located between the first die and the land side of the substrate.
摘要翻译： 一种装置包括具有接地侧的衬底，该接地侧具有多个接触焊盘和与接地侧相对的管芯侧。 该装置包括第一管芯和第二管芯，其中第一管芯和第二管芯被嵌入衬底内，使得第二管芯位于第一管芯和衬底的焊盘侧之间。
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2.发明授权Wafer level package with embedded passive components and method of manufacturing 有权晶圆级封装带嵌入式无源元件及制造方法公开(公告)号：US08680683B1
公开(公告)日：2014-03-25
申请号：US12957004
申请日：2010-11-30
CPC分类号： H01L23/5389 , H01L21/561 , H01L21/568 , H01L23/3114 , H01L23/49822 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/82 , H01L25/16 , H01L2224/24195 , H01L2224/24265 , H01L2224/251 , H01L2224/2518 , H01L2224/82005 , H01L2224/821 , H01L2924/1461 , H01L2924/181 , H01L2924/00014 , H01L2924/00
摘要： A wafer level package includes an epoxy layer formed on an adhesive covered substrate during manufacturing for securing electrical components in place prior to being embedded in a molded material. An electrically conductive block is fixed in the epoxy layer. Vias are formed for accessing face up component contacts using a metalized layer on the surface of the molded material. After stripping the adhesive and substrate, the epoxy layer is penetrated to expose electrical contacts for face down components. An electrical connection is made between the face up and face down components using the block. Optionally, a dielectric layer covers the molded material and a second metalized layer placed on the dielectric layer to carry another electrical component embedded in a second dielectric layer covering the first dielectric layer. Thus a stacked component arrangement including multiple die and passive components is effectively fabricated into the wafer level package.
摘要翻译： 晶片级封装包括在制造期间在粘合剂覆盖的基板上形成的环氧树脂层，以在嵌入模制材料之前将电气部件固定就位。 导电块固定在环氧树脂层中。 形成通孔，以便在模制材料的表面上使用金属化层来访问面朝上的组件触点。 在剥离粘合剂和基材之后，环氧树脂层被穿透以露出用于面朝下部件的电触头。 使用该块在面朝上和正面朝下的部件之间进行电连接。 可选地，电介质层覆盖模制材料和置于电介质层上的第二金属化层，以承载嵌入覆盖第一电介质层的第二电介质层中的另一电子部件。 因此，包括多个管芯和无源部件的堆叠部件布置被有效地制造到晶片级封装中。
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3.发明授权Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby 有权形成完全嵌入的无凸起积聚层包装的方法和由此形成的结构公开(公告)号：US08304913B2
公开(公告)日：2012-11-06
申请号：US12890045
申请日：2010-09-24
IPC分类号： H01L23/48
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/93 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/21 , H01L2224/2101 , H01L2224/211 , H01L2224/22 , H01L2224/2201 , H01L2224/221 , H01L2224/24011 , H01L2224/24146 , H01L2224/251 , H01L2224/25105 , H01L2224/2518 , H01L2224/73267 , H01L2224/82005 , H01L2224/821 , H01L2224/82101 , H01L2224/82106 , H01L2224/93 , H01L2225/06524 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/014 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2224/82 , H01L2221/68304 , H01L2924/00
摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.
摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括嵌入在无芯基板中的模具，其中模具化合物围绕模头，并且其中模具包括在第一侧上的TSV连接和在模具的第二侧上的C4焊盘，在第一侧上的电介质材料， 在模具化合物的第二面上; 以及耦合到C4焊盘和TSV焊盘的互连结构。 实施例还包括形成其中多个管芯完全嵌入在不具有PoP焊盘的BBUL封装内的封装结构。
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4.发明申请MULTI-CHIP PACKAGE HAVING A SUBSTRATE WITH A PLURALITY OF VERTICALLY EMBEDDED DIE AND A PROCESS OF FORMING THE SAME 审中-公开具有多个垂直嵌件的基片的多芯片封装及其形成方法公开(公告)号：US20140248742A1
公开(公告)日：2014-09-04
申请号：US14279165
申请日：2014-05-15
IPC分类号： H01L25/00
CPC分类号： H01L25/50 , H01L21/568 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/95 , H01L2224/12105 , H01L2224/19 , H01L2224/221 , H01L2224/2402 , H01L2224/24105 , H01L2224/24137 , H01L2224/24147 , H01L2224/245 , H01L2224/251 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/82005 , H01L2224/82039 , H01L2224/82101 , H01L2224/92244 , H01L2224/95 , H01L2224/95001 , H01L2924/00013 , H01L2924/01006 , H01L2924/01029 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1815 , H01L2924/18162 , H01L2224/82 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first die and a second die wherein the first die and second die are embedded within the substrate such that the second die is located between the first die and the land side of the substrate.
摘要翻译： 一种装置包括具有接地侧的衬底，该接地侧具有多个接触焊盘和与接地侧相对的管芯侧。 该装置包括第一管芯和第二管芯，其中第一管芯和第二管芯被嵌入衬底内，使得第二管芯位于第一管芯和衬底的焊盘侧之间。
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5.发明申请METHODS OF FORMING FULLY EMBEDDED BUMPLESS BUILD-UP LAYER PACKAGES AND STRUCTURES FORMED THEREBY 有权形成完整的嵌入式BUILD-LETER包和其结构的方法公开(公告)号：US20120074580A1
公开(公告)日：2012-03-29
申请号：US12890045
申请日：2010-09-24
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/93 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/21 , H01L2224/2101 , H01L2224/211 , H01L2224/22 , H01L2224/2201 , H01L2224/221 , H01L2224/24011 , H01L2224/24146 , H01L2224/251 , H01L2224/25105 , H01L2224/2518 , H01L2224/73267 , H01L2224/82005 , H01L2224/821 , H01L2224/82101 , H01L2224/82106 , H01L2224/93 , H01L2225/06524 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/014 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2224/82 , H01L2221/68304 , H01L2924/00
摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.
摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括嵌入在无芯基板中的模具，其中模具化合物围绕模具，并且其中模具包括在第一侧上的TSV连接和在模具的第二侧上的C4焊盘，在第一侧上的电介质材料， 在模具化合物的第二面上; 以及耦合到C4焊盘和TSV焊盘的互连结构。 实施例还包括形成其中多个管芯完全嵌入在不具有PoP焊盘的BBUL封装内的封装结构。
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6.发明授权Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same 有权具有具有多个垂直嵌入的裸片的基板的多芯片封装及其形成工艺公开(公告)号：US09559088B2
公开(公告)日：2017-01-31
申请号：US14279165
申请日：2014-05-15
IPC分类号： H01L25/00 , H01L23/538 , H01L23/00 , H01L23/498 , H01L21/56
CPC分类号： H01L25/50 , H01L21/568 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/95 , H01L2224/12105 , H01L2224/19 , H01L2224/221 , H01L2224/2402 , H01L2224/24105 , H01L2224/24137 , H01L2224/24147 , H01L2224/245 , H01L2224/251 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/82005 , H01L2224/82039 , H01L2224/82101 , H01L2224/92244 , H01L2224/95 , H01L2224/95001 , H01L2924/00013 , H01L2924/01006 , H01L2924/01029 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1815 , H01L2924/18162 , H01L2224/82 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first die and a second die wherein the first die and second die are embedded within the substrate such that the second die is located between the first die and the land side of the substrate.
摘要翻译： 一种装置包括具有接地侧的衬底，该接地侧具有多个接触焊盘和与接地侧相对的管芯侧。 该装置包括第一管芯和第二管芯，其中第一管芯和第二管芯被嵌入衬底内，使得第二管芯位于第一管芯和衬底的焊盘侧之间。
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7.发明授权Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby 有权形成完全嵌入的无凸起积聚层包装的方法和由此形成的结构公开(公告)号：US08580616B2
公开(公告)日：2013-11-12
申请号：US13629931
申请日：2012-09-28
IPC分类号： H01L21/00
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/93 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/21 , H01L2224/2101 , H01L2224/211 , H01L2224/22 , H01L2224/2201 , H01L2224/221 , H01L2224/24011 , H01L2224/24146 , H01L2224/251 , H01L2224/25105 , H01L2224/2518 , H01L2224/73267 , H01L2224/82005 , H01L2224/821 , H01L2224/82101 , H01L2224/82106 , H01L2224/93 , H01L2225/06524 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/014 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2224/82 , H01L2221/68304 , H01L2924/00
摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.
摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括嵌入在无芯基板中的模具，其中模具化合物围绕模头，并且其中模具包括在第一侧上的TSV连接和在模具的第二侧上的C4焊盘，在第一侧上的电介质材料， 在模具化合物的第二面上; 以及耦合到所述C4焊盘和所述TSV焊盘的互连结构。 实施例还包括形成其中多个管芯完全嵌入BBUL封装中而不具有PoP焊盘的封装结构。
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8.发明申请METHODS OF FORMING FULLY EMBEDDED BUMPLESS BUILD-UP LAYER PACKAGES AND STRUCTURES FORMED THEREBY 有权形成完整的嵌入式BUILD-LETER包和其结构的方法公开(公告)号：US20130023088A1
公开(公告)日：2013-01-24
申请号：US13629931
申请日：2012-09-28
IPC分类号： H01L21/50
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/93 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/21 , H01L2224/2101 , H01L2224/211 , H01L2224/22 , H01L2224/2201 , H01L2224/221 , H01L2224/24011 , H01L2224/24146 , H01L2224/251 , H01L2224/25105 , H01L2224/2518 , H01L2224/73267 , H01L2224/82005 , H01L2224/821 , H01L2224/82101 , H01L2224/82106 , H01L2224/93 , H01L2225/06524 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/014 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2224/82 , H01L2221/68304 , H01L2924/00
摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.
摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括嵌入在无芯基板中的模具，其中模具化合物围绕模头，并且其中模具包括在第一侧上的TSV连接和在模具的第二侧上的C4焊盘，在第一侧上的电介质材料， 在模具化合物的第二面上; 以及耦合到C4焊盘和TSV焊盘的互连结构。 实施例还包括形成其中多个管芯完全嵌入在不具有PoP焊盘的BBUL封装内的封装结构。
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9.发明申请公开(公告)号：US20120161331A1
公开(公告)日：2012-06-28
申请号：US12976903
申请日：2010-12-22
CPC分类号： H01L25/50 , H01L21/568 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/95 , H01L2224/12105 , H01L2224/19 , H01L2224/221 , H01L2224/2402 , H01L2224/24105 , H01L2224/24137 , H01L2224/24147 , H01L2224/245 , H01L2224/251 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/82005 , H01L2224/82039 , H01L2224/82101 , H01L2224/92244 , H01L2224/95 , H01L2224/95001 , H01L2924/00013 , H01L2924/01006 , H01L2924/01029 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1815 , H01L2924/18162 , H01L2224/82 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first die and a second die wherein the first die and second die are embedded within the substrate such that the second die is located between the first die and the land side of the substrate.
摘要翻译： 一种装置包括具有接地侧的衬底，该接地侧具有多个接触焊盘和与接地侧相对的管芯侧。 该装置包括第一管芯和第二管芯，其中第一管芯和第二管芯被嵌入衬底内，使得第二管芯位于第一管芯和衬底的焊盘侧之间。
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