公开(公告)号：US20160133590A1

公开(公告)日：2016-05-12

申请号：US14998093

申请日：2015-12-23

申请人： Pramod MALATKAR ,  Weng Hong TEH ,  John S. GUZEK ,  Robert L. SANKMAN

发明人： Pramod MALATKAR ,  Weng Hong TEH ,  John S. GUZEK ,  Robert L. SANKMAN

IPC分类号： H01L23/00 ,  H01L23/538

CPC分类号： H01L24/09 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/97 ,  H01L27/08 ,  H01L2224/04105 ,  H01L2224/08235 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

摘要： A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

摘要翻译： 描述了具有无冲击的模具 - 封装接口和制造方法的封装的半导体管芯。 例如，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中并且具有最上层的导电线，其中之一直接连接到衬底的导电通孔的最下层的导电通孔。 在另一示例中，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中，并且具有最上层的导电线，其上设置有导电通孔层。 导电线中的至少一个直接耦合到半导体管芯的导电通孔，该导电通孔直接连接到衬底的导电通路的最下层的导电通孔。

公开(公告)号：US20140239510A1

公开(公告)日：2014-08-28

申请号：US14269318

申请日：2014-05-05

申请人： Pramod Malatkar

发明人： Pramod Malatkar

IPC分类号： H01L23/00 ,  H01L23/522

CPC分类号： H01L24/83 ,  H01L21/568 ,  H01L23/29 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/538 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L41/083 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/80001 ,  H01L2224/83951 ,  H01L2224/92224 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00

摘要： The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

摘要翻译： 本公开涉及集成电路封装设计的领域，更具体地，涉及使用无凸起的构建层（BBUL）设计的封装。 本发明的实施例涉及制造微电子封装的领域，其中具有通硅通孔的第一微电子器件可以与第二微电子器件堆叠并且用于无扰性积聚层封装中。

公开(公告)号：US20130270715A1

公开(公告)日：2013-10-17

申请号：US13996495

申请日：2011-12-15

申请人： Pramod Malatkar ,  Weng Hong Teh ,  John S. Guzek ,  Robert L. Sankman

发明人： Pramod Malatkar ,  Weng Hong Teh ,  John S. Guzek ,  Robert L. Sankman

IPC分类号： H01L23/48

CPC分类号： H01L24/09 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/97 ,  H01L27/08 ,  H01L2224/04105 ,  H01L2224/08235 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

摘要： A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

摘要翻译： 描述了具有无冲击的模具 - 封装接口和制造方法的封装的半导体管芯。 例如，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中并且具有最上层的导电线，其中之一直接连接到衬底的导电通孔的最下层的导电通孔。 在另一示例中，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中，并且具有最上层的导电线，其上设置有导电通孔层。 导电线中的至少一个直接耦合到半导体管芯的导电通孔，该导电通孔直接连接到衬底的导电通路的最下层的导电通孔。

公开(公告)号：US08304913B2

公开(公告)日：2012-11-06

申请号：US12890045

申请日：2010-09-24

申请人： Ravi K Nalla ,  Pramod Malatkar ,  Mathew J Manusharow

发明人： Ravi K Nalla ,  Pramod Malatkar ,  Mathew J Manusharow

IPC分类号： H01L23/48

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/93 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/22 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/251 ,  H01L2224/25105 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/93 ,  H01L2225/06524 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2221/68304 ,  H01L2924/00

摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.

摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括嵌入在无芯基板中的模具，其中模具化合物围绕模头，并且其中模具包括在第一侧上的TSV连接和在模具的第二侧上的C4焊盘，在第一侧上的电介质材料， 在模具化合物的第二面上; 以及耦合到C4焊盘和TSV焊盘的互连结构。 实施例还包括形成其中多个管芯完全嵌入在不具有PoP焊盘的BBUL封装内的封装结构。

公开(公告)号：US20120001339A1

公开(公告)日：2012-01-05

申请号：US12827323

申请日：2010-06-30

申请人： Pramod Malatkar

发明人： Pramod Malatkar

IPC分类号： H01L23/538 ,  H01L21/60

CPC分类号： H01L24/96 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/12 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06135 ,  H01L2224/06155 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15172 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2224/05552 ,  H01L2924/00

摘要： The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein an interposer, such as a through-silicon via interposer, may be used in a bumpless build-up layer package to facilitate stacked microelectronic components.

摘要翻译： 本公开涉及集成电路封装设计的领域，更具体地，涉及使用无凸起的构建层（BBUL）设计的封装。 本说明书的实施例涉及制造微电子封装的领域，其中中间层，例如穿硅通孔插入件，可用于无扰性积聚层封装中，以便于堆叠的微电子元件。

公开(公告)号：US07179093B2

公开(公告)日：2007-02-20

申请号：US11174074

申请日：2005-06-30

申请人： Nicholas L. Holmberg ,  John J. Beatty ,  Pramod Malatkar

发明人： Nicholas L. Holmberg ,  John J. Beatty ,  Pramod Malatkar

IPC分类号： H01R13/62

CPC分类号： H05K7/1061 ,  H01R2201/20

摘要： In some embodiments, a retractable ledge socket is presented. In this regard, a socket ledge is introduced to receive a processor, and to reposition to allow the processor to contact socket connections. Other embodiments are also disclosed and claimed.

摘要翻译： 在一些实施例中，呈现可伸缩的突出插座。 在这方面，引入一个插座凸缘以接收一个处理器，并重新定位以允许处理器与插座连接接触。 还公开并要求保护其他实施例。

公开(公告)号：US20170287873A1

公开(公告)日：2017-10-05

申请号：US15084032

申请日：2016-03-29

申请人： Santosh Sankarasubramanian ,  Hong Xie ,  Nachiket R. Raravikar ,  Steven A. Klein ,  Pramod Malatkar

发明人： Santosh Sankarasubramanian ,  Hong Xie ,  Nachiket R. Raravikar ,  Steven A. Klein ,  Pramod Malatkar

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00

摘要： An IC package, an electronic assembly, and methods of preventing warpage of components of an electronic assembly during fabrication of the electronic assembly are shown. An IC package including an adhesive disposed at or near at least one of four corners of a die of the IC package is shown. An electronic assembly including an IC package that includes an adhesive disposed at or near at least one of four corners of a second surface of a first substrate is shown. Methods of preventing warpage of components of an electronic assembly during fabrication of the electronic assembly that include applying an adhesive to at least one of four corners of a first surface of a first component are shown.

公开(公告)号：US20140001623A1

公开(公告)日：2014-01-02

申请号：US13535905

申请日：2012-06-28

申请人： PRAMOD MALATKAR

发明人： PRAMOD MALATKAR

IPC分类号： H01L23/48 ,  H01L21/60 ,  H01L25/04 ,  H01L23/498

CPC分类号： H01L23/49833 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014

摘要： A microelectronic structure comprising a microelectronic package that includes at least one microelectronic device attached to a microelectronic interposer, wherein the microelectronic package is mounted to a microelectronic substrate, such that the microelectronic device is disposed between and in electrical communication with both the microelectronic interposer and the microelectronic substrate.

摘要翻译： 一种微电子结构，其包括微电子封装，其包括连接到微电子插入器的至少一个微电子器件，其中所述微电子封装安装到微电子衬底，使得所述微电子器件设置在微电子插入器和 微电子衬底。

公开(公告)号：US20120074580A1

公开(公告)日：2012-03-29

申请号：US12890045

申请日：2010-09-24

申请人： Ravi K. Nalla ,  Mathew J. Manusharow ,  Pramod Malatkar

发明人： Ravi K. Nalla ,  Mathew J. Manusharow ,  Pramod Malatkar

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/50

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/93 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/22 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/251 ,  H01L2224/25105 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/93 ,  H01L2225/06524 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2221/68304 ,  H01L2924/00

摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.

摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括嵌入在无芯基板中的模具，其中模具化合物围绕模具，并且其中模具包括在第一侧上的TSV连接和在模具的第二侧上的C4焊盘，在第一侧上的电介质材料， 在模具化合物的第二面上; 以及耦合到C4焊盘和TSV焊盘的互连结构。 实施例还包括形成其中多个管芯完全嵌入在不具有PoP焊盘的BBUL封装内的封装结构。

公开(公告)号：US20070004246A1

公开(公告)日：2007-01-04

申请号：US11174074

申请日：2005-06-30

申请人： Nicholas Holmberg ,  John Beatty ,  Pramod Malatkar

发明人： Nicholas Holmberg ,  John Beatty ,  Pramod Malatkar

IPC分类号： H01R12/00

CPC分类号： H05K7/1061 ,  H01R2201/20

摘要： In some embodiments, a retractable ledge socket is presented. In this regard, a socket ledge is introduced to receive a processor, and to reposition to allow the processor to contact socket connections. Other embodiments are also disclosed and claimed.

摘要翻译： 在一些实施例中，呈现可伸缩的突出插座。 在这方面，引入一个插座凸缘以接收一个处理器，并重新定位以允许处理器与插座连接接触。 还公开并要求保护其他实施例。