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1.发明申请METHODS OF FORMING FULLY EMBEDDED BUMPLESS BUILD-UP LAYER PACKAGES AND STRUCTURES FORMED THEREBY 有权形成完整的嵌入式BUILD-LETER包和其结构的方法公开(公告)号：US20120074580A1
公开(公告)日：2012-03-29
申请号：US12890045
申请日：2010-09-24
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/93 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/21 , H01L2224/2101 , H01L2224/211 , H01L2224/22 , H01L2224/2201 , H01L2224/221 , H01L2224/24011 , H01L2224/24146 , H01L2224/251 , H01L2224/25105 , H01L2224/2518 , H01L2224/73267 , H01L2224/82005 , H01L2224/821 , H01L2224/82101 , H01L2224/82106 , H01L2224/93 , H01L2225/06524 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/014 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2224/82 , H01L2221/68304 , H01L2924/00
摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.
摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括嵌入在无芯基板中的模具，其中模具化合物围绕模具，并且其中模具包括在第一侧上的TSV连接和在模具的第二侧上的C4焊盘，在第一侧上的电介质材料， 在模具化合物的第二面上; 以及耦合到C4焊盘和TSV焊盘的互连结构。 实施例还包括形成其中多个管芯完全嵌入在不具有PoP焊盘的BBUL封装内的封装结构。
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2.发明授权Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby 有权形成完全嵌入的无凸起积聚层包装的方法和由此形成的结构公开(公告)号：US08580616B2
公开(公告)日：2013-11-12
申请号：US13629931
申请日：2012-09-28
IPC分类号： H01L21/00
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/93 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/21 , H01L2224/2101 , H01L2224/211 , H01L2224/22 , H01L2224/2201 , H01L2224/221 , H01L2224/24011 , H01L2224/24146 , H01L2224/251 , H01L2224/25105 , H01L2224/2518 , H01L2224/73267 , H01L2224/82005 , H01L2224/821 , H01L2224/82101 , H01L2224/82106 , H01L2224/93 , H01L2225/06524 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/014 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2224/82 , H01L2221/68304 , H01L2924/00
摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.
摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括嵌入在无芯基板中的模具，其中模具化合物围绕模头，并且其中模具包括在第一侧上的TSV连接和在模具的第二侧上的C4焊盘，在第一侧上的电介质材料， 在模具化合物的第二面上; 以及耦合到所述C4焊盘和所述TSV焊盘的互连结构。 实施例还包括形成其中多个管芯完全嵌入BBUL封装中而不具有PoP焊盘的封装结构。
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3.发明申请LOW-PROFILE MICROELECTRONIC PACKAGE, METHOD OF MANUFACTURING SAME, AND ELECTRONIC ASSEMBLY CONTAINING SAME 审中-公开低剖面微电子封装，其制造方法和包含其的电子组件公开(公告)号：US20120139095A1
公开(公告)日：2012-06-07
申请号：US12959515
申请日：2010-12-03
CPC分类号： H01L23/564 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L23/36 , H01L23/3677 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L2221/68345 , H01L2221/68359 , H01L2221/68381 , H01L2224/04105 , H01L2224/12105 , H01L2224/73267 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/1815 , H01L2924/18162
摘要： A low-profile microelectronic package includes a die (110) (having a first surface (111) and a second surface (112)) and a package substrate (120). The substrate includes an electrically insulating layer (121) that forms a first side (126) of the substrate, an electrically conductive layer (122) connected to the die, and a protective layer (123) over the conductive layer that forms a second side (127) of the substrate. The first surface of the die is located at the first side of the substrate. The insulating layer has a plurality of pads (130) formed therein. The package further includes an array of interconnect structures (140) located at the first side of the substrate. Each interconnect structure in the array of interconnect structures has a first end (141) and a second end (142), and the first end is connected to one of the pads.
摘要翻译： 薄型微电子封装包括具有第一表面（111）和第二表面（112）的管芯（110）和封装衬底（120）。 衬底包括形成衬底的第一侧（126）的电绝缘层（121），连接到管芯的导电层（122）和形成第二侧的导电层上的保护层（123） （127）。 模具的第一表面位于基板的第一侧。 绝缘层具有形成在其中的多个焊盘（130）。 该封装还包括位于衬底第一侧的互连结构阵列（140）。 互连结构阵列中的每个互连结构具有第一端（141）和第二端（142），并且第一端连接到其中一个焊盘。
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4.发明授权Bumpless build-up layer and laminated core hybrid structures and methods of assembling same 有权无皱堆积层和层叠芯混合结构及其组装方法公开(公告)号：US08508037B2
公开(公告)日：2013-08-13
申请号：US12962358
申请日：2010-12-07
IPC分类号： H01L23/485
CPC分类号： H01L21/50 , H01L21/4857 , H01L21/486 , H01L23/3128 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2225/1035 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/1815 , H01L2924/18162 , H01L2924/3511 , H05K1/183 , H05K3/4641 , H01L2924/00
摘要： A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure.
摘要翻译： 一种结构包括用于支撑半导体器件的混合衬底，该半导体器件包括其中嵌入半导体器件的无凸起积聚层和层叠芯结构。 通过与层压芯结构中的电镀通孔连接的无刷构建层结构的后续接合焊盘的加强电镀将无凸起的堆积层和层叠芯结构作为一体的装置。
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公开(公告)号：US20130119544A1
公开(公告)日：2013-05-16
申请号：US13736209
申请日：2013-01-08
CPC分类号： H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/48 , H01L24/82 , H01L24/83 , H01L25/0655 , H01L25/105 , H01L2224/0401 , H01L2224/04105 , H01L2224/05009 , H01L2224/0557 , H01L2224/06181 , H01L2224/16225 , H01L2224/16227 , H01L2224/24137 , H01L2224/2518 , H01L2224/32245 , H01L2224/48227 , H01L2224/73267 , H01L2224/82105 , H01L2224/82106 , H01L2224/83203 , H01L2224/92244 , H01L2225/1035 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/30107 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (210), a first die (220) and a second die (260) embedded in the substrate and having a front side (221, 261) and a back side (222, 262) and a through-silicon-via (223, 263) therein, build-up layers (230) over the front sides of the first and second dies, and an electrically conductive structure (240) in physical contact with the back sides of the first and second dies.
摘要翻译： 微电子封装包括衬底（110），嵌入衬底内的管芯（120），管芯具有前侧（121）和后侧（122）以及贯通硅通孔（123） 在模具的前侧构建的上层（130）和与模具的背面物理接触的动力平面（140）。 在另一个实施例中，微电子封装包括衬底（210），嵌入衬底中的第一裸片（220）和第二裸片（260），并具有正面（221,261）和背面（222,262） 和其中的穿硅通孔（223,263），在第一和第二模具的前侧上方的堆积层（230），以及与第一和第二模具的背面物理接触的导电结构（240） 和第二个死亡。
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公开(公告)号：US20110316140A1
公开(公告)日：2011-12-29
申请号：US12825729
申请日：2010-06-29
IPC分类号： H01L23/538 , H01L21/60 , H01L23/48
CPC分类号： H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/48 , H01L24/82 , H01L24/83 , H01L25/0655 , H01L25/105 , H01L2224/0401 , H01L2224/04105 , H01L2224/05009 , H01L2224/0557 , H01L2224/06181 , H01L2224/16225 , H01L2224/16227 , H01L2224/24137 , H01L2224/2518 , H01L2224/32245 , H01L2224/48227 , H01L2224/73267 , H01L2224/82105 , H01L2224/82106 , H01L2224/83203 , H01L2224/92244 , H01L2225/1035 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/30107 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (210), a first die (220) and a second die (260) embedded in the substrate and having a front side (221, 261) and a back side (222, 262) and a through-silicon-via (223, 263) therein, build-up layers (230) over the front sides of the first and second dies, and an electrically conductive structure (240) in physical contact with the back sides of the first and second dies.
摘要翻译： 微电子封装包括衬底（110），嵌入衬底内的管芯（120），管芯具有前侧（121）和后侧（122）以及贯通硅通孔（123） 在模具的前侧构建的上层（130）和与模具的背面物理接触的动力平面（140）。 在另一个实施例中，微电子封装包括衬底（210），嵌入衬底中的第一裸片（220）和第二裸片（260），并具有正面（221,261）和背面（222,262） 和其中的穿硅通孔（223,263），在第一和第二模具的前侧上方的堆积层（230），以及与第一和第二模具的背面物理接触的导电结构（240） 和第二个死亡。
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公开(公告)号：US20110108999A1
公开(公告)日：2011-05-12
申请号：US12590350
申请日：2009-11-06
IPC分类号： H01L23/488 , H01L21/60
CPC分类号： H01L24/24 , H01L21/568 , H01L23/3128 , H01L24/16 , H01L24/48 , H01L24/82 , H01L25/0657 , H01L25/105 , H01L2224/04105 , H01L2224/16225 , H01L2224/16227 , H01L2224/19 , H01L2224/32145 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/10253 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/18162 , H01L2924/19107 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic package comprises a die (210) having attached thereto a first plurality of electrically conductive pads (211). The microelectronic package further comprises a first layer (220) and a second layer (130). The first layer has a first plurality of electrically conductive vias (121) electrically connected to one of the first plurality of electrically conductive pads. The second layer comprises a second plurality of electrically conductive pads (131) located around a perimeter (135) of the second layer and a plurality of electrically conductive traces (132) electrically connected to one of the first plurality of electrically conductive vias and to one of the second plurality of electrically conductive pads. The microelectronic package also comprises a plurality of wirebonds (240), each one of which is electrically connected to one of the second plurality of electrically conductive pads.
摘要翻译： 微电子封装包括具有附接到其上的第一多个导电焊盘（211）的管芯（210）。 微电子封装还包括第一层（220）和第二层（130）。 第一层具有电连接到第一多个导电焊盘之一的第一多个导电通孔（121）。 第二层包括位于第二层的周边（135）周围的第二多个导电焊盘（131），以及电连接到第一多个导电通孔之一的多个导电迹线（132）和一个 的第二多个导电焊盘。 微电子封装还包括多个引线键（240），其中每一个电连接到第二多个导电焊盘之一。
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公开(公告)号：US20110241195A1
公开(公告)日：2011-10-06
申请号：US12755183
申请日：2010-04-06
CPC分类号： H01L24/20 , H01L21/568 , H01L21/768 , H01L23/3107 , H01L23/34 , H01L23/36 , H01L23/367 , H01L23/481 , H01L23/49822 , H01L23/5389 , H01L24/19 , H01L2224/12105 , H01L2224/13021 , H01L2224/2101 , H01L2224/221 , H01L2224/24227 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H05K1/0209 , H05K1/185 , H05K3/4682
摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.
摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将管芯附接到载体材料，形成围绕管芯的电介质材料，在电介质材料中形成堆积层，以形成无芯无阻堆积的封装结构，以及图案化载体材料以在封装结构上形成微通道结构。
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公开(公告)号：US08896116B2
公开(公告)日：2014-11-25
申请号：US13736209
申请日：2013-01-08
IPC分类号： H01L23/34 , H01L23/48 , H01L23/538 , H01L25/065 , H01L23/00 , H01L25/10
CPC分类号： H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/48 , H01L24/82 , H01L24/83 , H01L25/0655 , H01L25/105 , H01L2224/0401 , H01L2224/04105 , H01L2224/05009 , H01L2224/0557 , H01L2224/06181 , H01L2224/16225 , H01L2224/16227 , H01L2224/24137 , H01L2224/2518 , H01L2224/32245 , H01L2224/48227 , H01L2224/73267 , H01L2224/82105 , H01L2224/82106 , H01L2224/83203 , H01L2224/92244 , H01L2225/1035 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/30107 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (210), a first die (220) and a second die (260) embedded in the substrate and having a front side (221, 261) and a back side (222, 262) and a through-silicon-via (223, 263) therein, build-up layers (230) over the front sides of the first and second dies, and an electrically conductive structure (240) in physical contact with the back sides of the first and second dies.
摘要翻译： 微电子封装包括衬底（110），嵌入衬底内的管芯（120），管芯具有前侧（121）和后侧（122）以及贯通硅通孔（123） 在模具的前侧构建的上层（130）和与模具的背面物理接触的动力平面（140）。 在另一个实施例中，微电子封装包括衬底（210），嵌入衬底中的第一裸片（220）和第二裸片（260），并具有正面（221,261）和背面（222,262） 和其中的穿硅通孔（223,263），在第一和第二模具的前侧上方的堆积层（230），以及与第一和第二模具的背面物理接触的导电结构（240） 和第二个死亡。
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10.发明申请LOW-PROFILE MICROELECTRONIC PACKAGE, METHOD OF MANUFACTURING SAME, AND ELECTRONIC ASSEMBLY CONTAINING SAME 审中-公开低剖面微电子封装，其制造方法和包含其的电子组件公开(公告)号：US20130228911A1
公开(公告)日：2013-09-05
申请号：US13848237
申请日：2013-03-21
IPC分类号： H01L23/00
CPC分类号： H01L23/564 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L23/36 , H01L23/3677 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L2221/68345 , H01L2221/68359 , H01L2221/68381 , H01L2224/04105 , H01L2224/12105 , H01L2224/73267 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/1815 , H01L2924/18162
摘要： A low-profile microelectronic package includes a die (110) (having a first surface (111) and a second surface (112)) and a package substrate (120). The substrate includes an electrically insulating layer (121) that forms a first side (126) of the substrate, an electrically conductive layer (122) connected to the die, and a protective layer (123) over the conductive layer that forms a second side (127) of the substrate. The first surface of the die is located at the first side of the substrate. The insulating layer has a plurality of pads (130) formed therein. The package further includes an array of interconnect structures (140) located at the first side of the substrate. Each interconnect structure in the array of interconnect structures has a first end (141) and a second end (142), and the first end is connected to one of the pads.
摘要翻译： 薄型微电子封装包括具有第一表面（111）和第二表面（112）的管芯（110）和封装衬底（120）。 衬底包括形成衬底的第一侧（126）的电绝缘层（121），连接到管芯的导电层（122）和形成第二侧的导电层上的保护层（123） （127）。 模具的第一表面位于基板的第一侧。 绝缘层具有形成在其中的多个焊盘（130）。 该封装还包括位于衬底第一侧的互连结构阵列（140）。 互连结构阵列中的每个互连结构具有第一端（141）和第二端（142），并且第一端连接到其中一个焊盘。
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