摘要:
A driver circuit comprises a driver portion, differential voltage input terminals, feedback circuitry, and differential voltage output terminals. The feedback circuitry connects a sample portion of the driver portion to a mixer portion of the driver portion. The sample portion may comprise an internal connection to the driver portion, for example, at a midpoint between differential outputs by the driver portion before regulation of the same differential voltages.
摘要:
The present invention relates to a transimpedance amplifier circuit that includes a linearized differential transimpedance amplifier, a detector, and dynamic current source circuitry, which diverts common mode currents from feedback resistors in the linearized differential transimpedance amplifier to keep the linearized differential transimpedance amplifier in a linear operating range. Magnitudes of the diverted common mode currents from the feedback resistors may be based on a detected magnitude associated with differential input signals that feed the linearized differential transimpedance amplifier. The detector provides a detector output signal to the dynamic current source circuitry based on the detected magnitude associated with the differential input signals, such that the diverted common mode currents are based on the detector output signal. The transimpedance amplifier circuit provides differential output signals that are based on amplifying the differential input signals.
摘要:
A differential amplification circuit includes a differential amplifier and common mode control circuitry configured to control output common mode of the differential amplifier. However, this control circuitry does not use feedback. The circuitry controls the output common mode in either, or in a combination of two ways, neither of which employs feedback from the output common mode. One control technique uses a dummy circuit and comparator to cancel out the effect of variations in process, temperature and supply voltage on output common mode. Another control technique measures input common mode voltage, compares the measured common mode to a reference, and based on the difference, applies a current to the output that compensates for the variation in output common mode that a given input common mode would otherwise cause.
摘要:
A slew rate improved operational amplifier circuit is provided to improve the slew rates of an operational amplifier with minimal sacrifices in power dissipation and other operational amplifier parameters. To improve the slew rates of operational amplifiers, additional current sources are activated when a slewing operation is detected. The detection of slewing operations and the activation of current sources upon detection can be implemented using two comparator circuits—one for a positive slewing operation, and one for a negative slewing operation. A sub-45 nm FinFET implementation of this slew rate improvement concept was implemented and compared against slew rate optimized individual two-stage operational amplifiers. Simulations show that slew rates were significantly improved by the implementation of the comparator circuits (5590 V/μs vs. 273 V/μs), with minimal increases in power dissipation (78 μW vs. 46 μW).
摘要翻译:提供了一种转换速率改进的运算放大器电路,以便以最小的功耗牺牲和其他运算放大器参数来提高运算放大器的转换速率。 为了提高运算放大器的转换速率,当检测到回转操作时,会激活额外的电流源。 检测到的回转操作和电流源的检测可以使用两个比较器电路实现,一个用于正回转操作,另一个用于负回转操作。 实现了这种转换速率改进概念的45纳米FinFET实现,并将其与转换速率优化的单个两级运算放大器进行比较。 模拟显示,通过实施比较器电路(5590 V /μsvs. 273 V /μs),转换速率得到显着提高,功耗增加最小(78μW至46μW)。
摘要:
A slew rate improved operational amplifier circuit is provided to improve the slew rates of an operational amplifier with minimal sacrifices in power dissipation and other operational amplifier parameters. To improve the slew rates of operational amplifiers, additional current sources are activated when a slewing operation is detected. The detection of slewing operations and the activation of current sources upon detection can be implemented using two comparator circuits—one for a positive slewing operation, and one for a negative slewing operation. A sub-45 nm FinFET implementation of this slew rate improvement concept was implemented and compared against slew rate optimized individual two-stage operational amplifiers. Simulations show that slew rates were significantly improved by the implementation of the comparator circuits (5590 V/μs vs. 273 V/μs), with minimal increases in power dissipation (78 μW vs. 46 μW).
摘要翻译:提供了一种转换速率改进的运算放大器电路,以便以最小的功耗牺牲和其他运算放大器参数来提高运算放大器的转换速率。 为了提高运算放大器的转换速率,当检测到回转操作时,会激活额外的电流源。 检测到的回转操作和电流源的检测可以使用两个比较器电路实现,一个用于正回转操作,另一个用于负回转操作。 实现了这种转换速率改进概念的45纳米FinFET实现,并将其与转换速率优化的单个两级运算放大器进行比较。 模拟显示,通过实施比较器电路(5590 V /μsvs. 273 V /μs),转换速率得到显着提高,功耗增加最小(78μW至46μW)。
摘要:
A circuit comprises a first amplifier portion and a second amplifier portion. The first amplifier portion includes first and second transistors coupled together in a common-base configuration. A current mirror is coupled to the first and second transistors. A first filter is coupled between a first input and the first and second transistors. The second amplifier portion includes third and fourth transistors coupled together in a common-base configuration. First and second current sources are coupled to the third and fourth transistors. A second filter is coupled between a second input and the control electrodes of the third and fourth transistors, wherein the first and second filters are coupled together.
摘要:
A high gain transistor amplifier with internal balancing bias having a common mode input range which includes a supply rail includes a differential to single-ended converting input stage including at least one pair of transistors, each transistor having first and second current terminals and a control terminal; input means for providing an input signal to the first current terminals of the transistors; a voltage amplifier stage for providing an amplified output of the input signal, the voltage amplifier stage including at least one transistor having a control terminal; and a biasing circuit responsive to the voltage amplifier stage for maintaining balanced currents between the control terminal of the voltage amplifier stage and the control terminals of the differential to single-ended converting input stage, the biasing circuit being connected to the second current terminals of each transistor pair and the voltage amplifier stage being connected to one of the second current terminals so that the first terminal may be driven in a common mode potential range which includes a supply rail.
摘要:
The differential amplifier current folder circuit of the present invention employs dynamic biasing to provide supplemental bias currents to the collector-emitter paths of the differential amplifier transistors in proportion to the magnitude of the input signal. Since the bias current through the main coding path comprising the coding and weighting network is thus determined only by the magnitude of the input signal and not by the magnitude of a bias current predetermined in accordance with expected peak magnitude input signals, the I Delta R voltage drop and leakage currents in the folder circuit are proportional to the magnitude of the input signal. Lower magnitude input signals can thus be coded with a minimum of error using either thin film techniques or components readily available from commercial sources.