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公开(公告)号：US10295580B2
公开(公告)日：2019-05-21
申请号：US15284374
申请日：2016-10-03
Applicant: Analog Devices Global
Inventor： Vamshi Krishna Chillara , Pablo Cruz Dato , Declan M. Dalton
Abstract: A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.
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公开(公告)号：US20190305785A1
公开(公告)日：2019-10-03
申请号：US15942119
申请日：2018-03-30
Applicant: Analog Devices Global Unlimited Company
Inventor： Vamshi Krishna Chillara , Declan M. Dalton , Pablo Cruz Dato
Abstract: Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal.
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Patent Agency Ranking
公开(公告)号：US20180097522A1
公开(公告)日：2018-04-05
申请号：US15284190
申请日：2016-10-03
Applicant: Analog Devices Global
Inventor： Vamshi Krishna Chillara , Declan M. Dalton , Pablo Cruz Dato
CPC classification number: H03L7/093 , H03K3/80 , H03K4/90 , H03L7/0991 , H03L7/104 , H03L7/107 , H03L7/12 , H03L2207/06
Abstract: Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.
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公开(公告)号：US10931290B2
公开(公告)日：2021-02-23
申请号：US15942119
申请日：2018-03-30
Applicant: Analog Devices Global Unlimited Company
Inventor： Vamshi Krishna Chillara , Declan M. Dalton , Pablo Cruz Dato
Abstract: Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal.
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公开(公告)号：US20180095119A1
公开(公告)日：2018-04-05
申请号：US15284374
申请日：2016-10-03
Applicant: Analog Devices Global
Inventor： Vamshi Krishna Chillara , Pablo Cruz Dato , Declan M. Dalton
CPC classification number: G01R23/02 , H03L7/08 , H03L7/091 , H03L7/0993 , H03L7/1075 , H03L2207/50
Abstract: A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.
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公开(公告)号：US10340926B2
公开(公告)日：2019-07-02
申请号：US15284190
申请日：2016-10-03
Applicant: Analog Devices Global
Inventor： Vamshi Krishna Chillara , Declan M. Dalton , Pablo Cruz Dato
Abstract: Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.
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公开(公告)号：US09893734B1
公开(公告)日：2018-02-13
申请号：US15284195
申请日：2016-10-03
Applicant: Analog Devices Global
Inventor： Vamshi Krishna Chillara , Declan M. Dalton
CPC classification number: H03L7/07 , H03L7/091 , H03L7/0994 , H03L7/22 , H03L2207/50
Abstract: Aspects of this disclosure relate to a digital phase-locked loop (DPLL) arranged to adjust output phase using a phase adjustment signal. In certain embodiments, the phase adjustment signal can be received in a signal path from an output of a time-to-digital converter of the DPLL to an input to the digitally controlled oscillator of the DPLL. Some embodiments relate to adjusting the output phase of the DPLL to reduce a relative phase difference between the output phase of the DPLL and an output phase of another DPLL.
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