公开(公告)号：US20040104455A1

公开(公告)日：2004-06-03

申请号：US10430291

申请日：2003-05-07

申请人： MITSUBISHI DENKI KABUSHIKI KAISHA

发明人： Kazuhiro Shimizu

IPC分类号： H01L023/552

CPC分类号： H01L23/5225 ,  H01L23/60 ,  H01L27/0629 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7816 ,  H01L2924/0002 ,  H01L2924/00

摘要： A floating electrode (201) and an electrode (202) are coupled together by an electrostatic capacitance (C1), the floating electrode (201) and an electrode (203) are coupled together by an electrostatic capacitance (C2), and an electrode (200) and the floating electrode (201) are coupled together by an electrostatic capacitance (C3). The potential of the floating electrode (201) is lower than the potential applied to the electrode (200). The floating electrode (201) covers above the electrode (200). For example, as viewed in section, the elevation angles (null, null) of widthwise edges of the electrode (201) from the near widthwise edges of the electrode (200) should preferably be not more than 45 degrees.

摘要翻译： 浮动电极（201）和电极（202）通过静电电容（C1）耦合在一起，浮动电极（201）和电极（203）通过静电电容（C2）和电极（C2）耦合在一起 200），并且浮动电极（201）通过静电电容（C3）耦合在一起。 浮置电极（201）的电位低于施加到电极（200）的电位。 浮动电极（201）覆盖电极（200）上方。 例如，如图所示，电极（201）从电极（200）的近宽边方向的边缘的宽度方向边缘的仰角（α，β）优选地应不大于45度。

公开(公告)号：US20030209783A1

公开(公告)日：2003-11-13

申请号：US10369114

申请日：2003-02-18

申请人： STMicroelectronics S.r.I.

发明人： Paolo Casati ,  Amedeo Maierna ,  Bruno Murari

IPC分类号： H01L023/552

CPC分类号： H01L23/49568 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/552 ,  H01L2224/83855 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/3025

摘要： An assembly structure for an electronic integrated power circuit, which circuit is fabricated on a semiconductor die having a plurality of contact pads associated with said integrated circuit and connected electrically to respective leads of said structure, wherein a shield element is coupled thermally to said die by a layer of an adhesive material.

摘要翻译： 一种用于电子集成电力电路的组装结构，该电路制造在具有与所述集成电路相关联的多个接触焊盘并且电连接到所述结构的相应引线的半导体管芯上，其中屏蔽元件通过 一层粘合剂材料。

公开(公告)号：US20030015772A1

公开(公告)日：2003-01-23

申请号：US09911364

申请日：2001-07-23

发明人： Tony G. Ivanov ,  Michael S. Carroll ,  Ranbir Singh

IPC分类号： H01L023/552 ,  H01L039/00 ,  H01L029/40

CPC分类号： H01L21/76251 ,  H01L23/5283 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for electromagnetically shielding circuits which combine to form an integrated circuit device provides isolated silicon islands surrounded laterally and subjacently by conductive material. The isolated silicon islands may be covered individually or as a group by a conductive cover. The integrated circuit may include at least one silicon island including an analog circuit and at least one silicon island including a digital circuit, the analog and digital circuits electromagnetically shielded from one another. The method for forming the structure includes providing a first semiconductor substrate and hydrophilically bonding a substructure to the first semiconductor substrate. The substructure includes the isolated silicon islands surrounded by the conductive material. The substructure may be formed on a second semiconductor substrate by implanting an impurity region into an upper portion of the second semiconductor substrate. After bonding, the substructure may be separated from the remainder of the second substrate by propagating a crack along the boundary of the impurity region which separates the substructure from the remainder of the second semiconductor substrate. The method further includes forming the conductive cover over the isolated silicon island or islands by forming insulating layers over the silicon islands then forming a conductive cover layer and conductive sidewalls to surround the silicon island or islands being enclosed.

摘要翻译： 组合形成集成电路器件的电磁屏蔽电路的方法提供了隔离的硅岛，其横向地和由传导材料邻接地包围。 孤立的硅岛可以单独地覆盖或通过导电覆盖物覆盖。 集成电路可以包括至少一个包括模拟电路的硅岛和包括数字电路的至少一个硅岛，模拟和数字电路彼此电磁屏蔽。 形成该结构的方法包括提供第一半导体衬底并将子结构亲水地结合到第一半导体衬底。 该子结构包括由导电材料包围的隔离的硅岛。 可以通过将杂质区注入到第二半导体衬底的上部中而在第二半导体衬底上形成子结构。 在结合之后，通过沿着将子结构与第二半导体衬底的其余部分分离的杂质区域的边界传播裂纹，子结构可以与第二衬底的其余部分分离。 该方法还包括通过在硅岛上方形成绝缘层，形成导电覆盖层和导电侧壁以围绕被隔离的硅岛或岛状物，在隔离的硅岛或岛上形成导电盖。

公开(公告)号：US20010009281A1

公开(公告)日：2001-07-26

申请号：US09749574

申请日：2000-12-28

发明人： Jeong-Kweon Park

IPC分类号： H01L021/4763 ,  H01L021/44 ,  H01L033/00 ,  H01L031/062 ,  H01L031/113 ,  H01L031/0232 ,  H01L023/552

CPC分类号： G03F1/32

摘要： A phase shift mask and a fabrication method thereof are used in a semiconductor light exposing process, where a CD (Critical Dimension) formed on a wafer is the same in all directions, even when a pattern is arranged on the mask at an anisotropic pitch. The phase shift mask includes a number of light transmitting regions and first and second phase shift regions arranged among the light transmitting regions. The first and second phase shift regions have a refractive index different from that of the light transmitting region. The first and second phase shift regions also have a transmittance different from each other.

摘要翻译： 在半导体光曝光工艺中使用相移掩模及其制造方法，其中形成在晶片上的CD（临界尺寸）在所有方向上相同，即使当以各向异性间距将掩模布置在图案上时。 相移掩模包括多个透光区域和布置在光透射区域之间的第一和第二相移区域。 第一和第二相移区域具有与透光区域不同的折射率。 第一和第二相移区域也具有彼此不同的透射率。

公开(公告)号：US20040155320A1

公开(公告)日：2004-08-12

申请号：US10365093

申请日：2003-02-12

发明人： Michael Clement DeJule ,  Ching-Yeu Wei ,  David Francis Fobare

IPC分类号： H01L021/00 ,  H01L031/0203 ,  H01L023/552 ,  G01T001/24

CPC分类号： G01T1/2018 ,  H01L27/14658 ,  H01L31/0216 ,  H01L31/115 ,  H01L31/18

摘要： A digital X-ray panel and method of fabricating an X-ray detector panel assembly is provided. The method includes forming a detector matrix on the detector substrate, forming a dam on the detector substrate circumscribing the detector matrix, forming a scintillator material on the detector matrix, and forming a hermetic covering on the scintillator material that at least one of extends to a surface of the dam and extends past the dam. The digital X-ray panel assembly includes a detector substrate, a detector matrix formed on said detector substrate, a dam formed on said detector substrate circumscribing the detector matrix, a scintillator material formed on the detector matrix, and a hermetic covering formed on the scintillator material that at least one of extends past the detector matrix and the dam, and extends past the detector matrix onto a surface of the dam.

摘要翻译： 提供数字X射线面板和制造X射线检测器面板组件的方法。 该方法包括在检测器基板上形成检测器矩阵，在检测器基板上形成围绕检测器矩阵的阻挡层，在检测器基体上形成闪烁体材料，并在闪烁体材料上形成气密覆盖物，其至少一个延伸到 大坝表面延伸穿过大坝。 所述数字X射线面板组件包括检测器基板，形成在所述检测器基板上的检测器矩阵，形成在所述检测器基板上的围绕所述检测器矩阵的阻挡层，形成在所述检测器矩阵上的闪烁体材料，以及形成在所述闪烁体上的气密盖 材料，其中至少一个延伸超过检测器矩阵和坝，并且延伸经过检测器矩阵到坝的表面上。

公开(公告)号：US20040145033A1

公开(公告)日：2004-07-29

申请号：US10626031

申请日：2003-07-23

发明人： Kenneth S. McElvain

IPC分类号： H01L023/552

CPC分类号： G06F17/5077 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment of the present invention, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

摘要翻译： 设计具有屏蔽线的集成电路（IC）的方法和装置。 在本发明的至少一个实施例中，使用至少两个参考电压（例如功率和接地）的屏蔽网来减小IC芯片中路由信号线中的电容耦合和电感耦合。 在一些实施例中，选择一种类型的屏蔽网格（例如，具有由电源环包围的窗口的屏蔽网格或具有解析器屏蔽线组的窗口）以使得在局部拥塞区域中可以获得更多的布线区域。 在其他实施例中，屏蔽网用于产生或添加旁路电容。 还公开了其他实施例。

公开(公告)号：US20040036150A1

公开(公告)日：2004-02-26

申请号：US10224794

申请日：2002-08-21

发明人： Bradley P. Smith ,  Edward O. Travis

IPC分类号： H01L023/552

CPC分类号： H01L23/552 ,  H01L2924/0002 ,  Y02P80/30 ,  H01L2924/00

摘要： A semiconductor device that has a common border between P and N wells is susceptible to photovoltaic current that is believed to be primarily generated from photons that strike this common border. Photons that strike the border are believed to create electron/hole pairs that separate when created at the PN junction of the border. The photovoltaic current can have a sufficient current density to be destructive to the metal connections to a well if the area of these metal connections to the well is small relative to the length of the border. This photovoltaic current can be reduced below destructive levels by covering the common border sufficiently to reduce the number of photons hitting the common border. The surface area of the connections can also be increased to alleviate the problem.

摘要翻译： 在P和N阱之间具有共同边界的半导体器件易于被认为主要由撞击该共同边界的光子产生的光电流。 据认为，在边界PN结处产生的电子/空穴对被分离出来。 如果与井的这些金属连接的面积相对于边界的长度小，则光电流可以具有足够的电流密度来破坏与阱的金属连接。 通过充分覆盖公共边界以减少击中共同边界的光子的数量，该光电流可以降低到破坏性水平以下。 连接的表面积也可以增加以减轻问题。

公开(公告)号：US20020167053A1

公开(公告)日：2002-11-14

申请号：US10143698

申请日：2002-05-08

发明人： Shao-Chang Huang

IPC分类号： H01L023/62 ,  H01L023/552

CPC分类号： H01L27/0251 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A CDM protection is provided within an internal device region of an integrated circuit where a plurality of working components are formed. The CDM protection circuit comprises a plurality of CDM protection devices that are electrically connected to one another, and a grounded conductive pad electrically connected to one CDM protection device, the CDM protection devices including a plurality of dummy devices such as dummy metals in tapered shape. The CDM protection devices are distributed over the internal device region in a manner to achieve a global protection of the IC against CDM charges by absorbing and dissipating the CDM charges. To increase CDM protection, a capacitor is further disposed in a manner to surround the internal device region.

摘要翻译： 在集成电路的内部设备区域内提供CDM保护，其中形成多个工作部件。 CDM保护电路包括彼此电连接的多个CDM保护装置和电连接到一个CDM保护装置的接地导电焊盘，CDM保护装置包括多个虚设装置，例如呈锥形的虚拟金属。 CDM保护装置以内部装置区域分布，以通过吸收和消散CDM费用来实现IC对CDM费用的全面保护。 为了增加CDM保护，电容器进一步以围绕内部装置区域的方式设置。

公开(公告)号：US20010040274A1

公开(公告)日：2001-11-15

申请号：US09525802

申请日：2000-03-15

发明人： Itsuo Hidaka

IPC分类号： H01L023/552

CPC分类号： H01L23/585 ,  H01L23/552 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/00

摘要： Two adjacent lines are formed in parallel to a signal line in a wiring layer where the signal line is formed. Intersection lines are formed respectively in wiring layers above and under the wiring layers where the signal line and the adjacent lines are formed, along areas which are enclosed by the adjacent lines. Entire-line-area through-holes for connecting each of the adjacent lines with a corresponding one of the intersection line are formed along the entire area of the adjacent lines, in an insulating layer between the adjacent lines and the intersection lines. The signal line is completely covered by the adjacent lines, the intersection lines and the entire-line-area through-holes. The adjacent lines, the intersection lines and the entire-line-area through-holes are maintained at a constant potential, or their electric potentials have the same phase as that of the signal line.

摘要翻译： 两条相邻的线与形成信号线的布线层中的信号线平行地形成。 在由相邻线包围的区域上分别形成交叉线，其中形成信号线和相邻线的布线层的上方和下方的布线层。 在相邻线和交叉线之间的绝缘层中，沿相邻线的整个区域形成用于连接相邻线中的每一条与相应一条相交线的整线区域通孔。 信号线完全被相邻线，交叉线和全线路通孔覆盖。 相邻的线，交叉线和全线区域通孔保持在恒定电位，或者它们的电位具有与信号线相同的相位。

公开(公告)号：US20040251522A1

公开(公告)日：2004-12-16

申请号：US10458130

申请日：2003-06-10

发明人： Severino A. Legaspi JR. ,  Manickam Thavarajah ,  Maurice O. Othieno ,  Pradip D. Patel

IPC分类号： H01L023/552

CPC分类号： H01L23/552 ,  H01L23/295 ,  H01L23/3135 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of shielding an integrated circuit from electromagnetic interference. The integrated circuit is at least partially encapsulated within an electromagnetic interference resistant molding compound, and then the integrated circuit is completely encapsulated within a second molding compound. In this manner, the electromagnetic interference resistant molding compound protects the integrated circuit from electromagnetic interference, while the second molding compound can be selected for properties traditionally desired in a molding compound, such as thermal, electrical insulating, and structural properties. Thus, the integrated circuit according to the present invention can be placed closer to structures, such as power supplies, which produce electromagnetic interference, without experiencing an unacceptable degradation of performance due to the electromagnetic interference caused by the structures.

摘要翻译： 一种屏蔽集成电路免受电磁干扰的方法。 集成电路至少部分地封装在耐电磁干扰模塑料中，然后将集成电路完全封装在第二模塑料中。 以这种方式，抗电磁干扰模塑料保护集成电路免受电磁干扰，而可以选择第二模塑料用于模塑料中传统上期望的性能，例如热，电绝缘和结构性能。 因此，根据本发明的集成电路可以更靠近产生电磁干扰的结构，例如电源，而不会由于由结构引起的电磁干扰而经受不可接受的性能劣化。