METHOD AND APPARATUS FOR ACCESSING INTERNAL NODES OF AN INTEGRATED CIRCUIT USING IC PACKAGE SUBSTRATE
    1.
    发明申请
    METHOD AND APPARATUS FOR ACCESSING INTERNAL NODES OF AN INTEGRATED CIRCUIT USING IC PACKAGE SUBSTRATE 有权
    使用IC封装基板访问集成电路内部节点的方法和装置

    公开(公告)号:US20040173878A1

    公开(公告)日:2004-09-09

    申请号:US10382343

    申请日:2003-03-04

    发明人: Kenneth Wilsher

    IPC分类号: H01L039/00 H01L029/40

    摘要: A method and apparatus for accessing internal nodes of an integrated circuit using a package substrate are provided. Embodiments of the present invention include an integrated circuit comprising an integrated circuit die comprising a principal side; a conductive element formed on the principal side of the integrated circuit die; a package substrate comprising a principal side facing the principal side of the integrated circuit die; a conductive element located on the principal side of the package substrate; a transmission path wherein a first end of the transmission path is coupled to the conductive element of the integrated circuit die and wherein a second end of the transmission path is coupled to the conductive element of the package substrate.

    摘要翻译: 提供一种用于访问使用封装衬底的集成电路的内部节点的方法和装置。 本发明的实施例包括集成电路,其包括:包括主侧的集成电路管芯; 形成在集成电路管芯的主面上的导电元件; 封装基板,其包括面向所述集成电路管芯的主面的主面; 位于所述封装基板的所述主面上的导电元件; 传输路径,其中传输路径的第一端耦合到集成电路管芯的导电元件,并且其中传输路径的第二端耦合到封装衬底的导电元件。

    SCHOTTKY BARRIER TUNNEL TRANSISTOR USING THIN SILICON LAYER ON INSULATOR AND METHOD FOR FABRICATING THE SAME
    3.
    发明申请
    SCHOTTKY BARRIER TUNNEL TRANSISTOR USING THIN SILICON LAYER ON INSULATOR AND METHOD FOR FABRICATING THE SAME 失效
    在绝缘体上使用薄硅层的肖特基栅栏式隧道式晶体管及其制造方法

    公开(公告)号:US20040026688A1

    公开(公告)日:2004-02-12

    申请号:US10331945

    申请日:2002-12-31

    摘要: Provided are a Schottky barrier tunnel transistor (SBTT) and a method of fabricating the same. The SBTT includes a buried oxide layer formed on a base substrate layer and having a groove at its upper surface; an ultra-thin silicon-on-insulator (SOI) layer formed across the groove; an insulating layer wrapping the SOI layer on the groove; a gate formed to be wider than the groove on the insulating layer; source and drain regions each positioned at both sides of the gate, the source and drain regions formed of silicide; and a conductive layer for filling the groove. In the SBTT, the SOI layer is formed to an ultra-thin thickness to minimize the occurrence of a leakage current, and a channel in the SOI layer below the gate is completely wrapped by the gate and the conductive layer, thereby improving the operational characteristics of the SBTT.

    摘要翻译: 提供了一种肖特基势垒隧道晶体管(SBTT)及其制造方法。 SBTT包括形成在基底层上并在其上表面具有凹槽的掩埋氧化物层; 跨越沟槽形成的超薄绝缘体上硅(SOI)层; 将SOI层包裹在槽上的绝缘层; 形成为比绝缘层上的沟槽宽的栅极; 源极和漏极区域各自位于栅极的两侧,源极和漏极区域由硅化物形成; 以及用于填充凹槽的导电层。 在SBTT中,SOI层形成为超薄的厚度,以最小化泄漏电流的发生,栅极下方的SOI层中的沟道被栅极和导电层完全包围,从而提高了操作特性 的SBTT。

    Semiconductor integrated circuit
    4.
    发明申请
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号:US20030178706A1

    公开(公告)日:2003-09-25

    申请号:US10388448

    申请日:2003-03-17

    申请人: Fujitsu Limited

    IPC分类号: H01L039/00

    摘要: A shield wiring is provided on a boundary of a target region to be shielded of macros, an inner side of the boundary, an outer side of the boundary, or an inner side and an outer side of the boundary, each being as a black box, so as to surround the target region. This shield wiring is electrically connected to a power supply terminal or a power supply wiring of the macros or the like, or to a power supply wiring on another wiring layer through a contact section, thereby fixing a potential of the shield wiring. An accurate delay value is then obtained by estimating an influence of crosstalk between a wiring in a region where the physical wiring pattern is clear and the shield wiring and also estimating a capacitance produced between the wirings.

    摘要翻译: 屏蔽布线设置在要被屏蔽的目标区域的边界上,边界的内侧,边界的外侧,边界的内侧和外侧,每个都是黑色框 ,以便围绕目标区域。 该屏蔽布线通过接触部分电连接到电源端子或宏等的电源布线,或者连接到另一布线层上的电源布线,从而固定屏蔽布线的电位。 然后通过估计物理布线图案清晰的区域中的布线与屏蔽布线之间的串扰的影响,并估计布线之间产生的电容,从而获得准确的延迟值。

    Superconducting PM undiffused machines with stationary superconducting coils
    6.
    发明申请
    Superconducting PM undiffused machines with stationary superconducting coils 失效
    具有固定超导线圈的超导PM未扩散机

    公开(公告)号:US20030094880A1

    公开(公告)日:2003-05-22

    申请号:US10339745

    申请日:2003-01-09

    CPC分类号: H02K21/38 H02K2201/12

    摘要: A superconducting PM machine has a stator, a rotor and a stationary excitation source without the need of a ferromagnetic frame which is cryogenically cooled for operation in the superconducting state. PM material is placed between poles on the rotor to prevent leakage or diffusion of secondary flux before reaching the main air gap, or to divert PM flux where it is desired to weaken flux in the main air gap. The PM material provides hop-along capability for the machine in the event of a fault condition.

    摘要翻译: 超导PM机具有定子,转子和固定激励源,而不需要用于在超导状态下进行低温冷却的铁磁框架。 PM材料放置在转子的两极之间,以防止在到达主气隙之前二次通量的泄漏或扩散,或者在需要削弱主空气间隙中的通量的情况下转移PM通量。 PM材料在故障情况下为机器提供跳跃功能。

    Flip chip assembly and method of producing flip chip assembly
    7.
    发明申请
    Flip chip assembly and method of producing flip chip assembly 失效
    倒装芯片组装及倒装芯片组装方法

    公开(公告)号:US20030015804A1

    公开(公告)日:2003-01-23

    申请号:US09910284

    申请日:2001-07-20

    摘要: A flip chip assembly is disclosed that includes a coplanar waveguide launch with a transmission line, and a bump interconnection that includes multiple ground bumps. The transmission line maybe a radial transmission line. Similarly, the ground bumps maybe arranged in a pseudo-coaxial configuration so as to effect a vertical transition in the flip chip assembly. A method is also disclosed that includes the steps of: providing a coplanar waveguide transmission line launch; providing a chip for attachment to the coplanar waveguide launch; arranging one or more ground bumps on the coplanar waveguide launch; and forming a bump interconnection between the coplanar waveguide launch and the chip. The coplanar waveguide launch provided in this step may include a radial transmission line. The step of arranging the multiple ground bumps may include the step of arranging multiple ground bumps in a pseudo-coaxial configuration.

    摘要翻译: 公开了一种倒装芯片组件,其包括具有传输线的共面波导发射和包括多个接地凸块的凸块互连。 传输线可以是径向传输线。 类似地,接地凸块可以以伪同轴结构布置,以便在倒装芯片组件中实现垂直转变。 还公开了一种方法,其包括以下步骤:提供共面波导传输线发射; 提供用于附接到共面波导发射的芯片; 在共面波导发射上布置一个或多个接地突起; 并在共面波导发射和芯片之间形成凸块互连。 在该步骤中提供的共面波导发射可以包括径向传输线。 布置多个接地凸块的步骤可以包括以伪同轴配置布置多个接地凸块的步骤。

    Method of forming a superconductor
    9.
    发明申请
    Method of forming a superconductor 审中-公开
    形成超导体的方法

    公开(公告)号:US20020119893A1

    公开(公告)日:2002-08-29

    申请号:US09950324

    申请日:2001-09-10

    摘要: Disclosed herein is a method of forming a superconductor, comprising the steps of: providing a substrate and exposing the substrate to a first atmosphere, including precursors to form a first epitaxial layer segment. The first layer segment is then exposed to a second atmosphere, including precursors to form a second epitaxial layer segment, and the second layer segment is exposed to a third atmosphere including precursors to form a third epitaxial layer segment. Each of the first and third layer segments are each formed from a superconductor material and the second layer segment is formed from a material different from the first and third layer segments and the first, second and third layer segments have a collective thickness, the third layer segment having an outer surface with a roughness which is less than that of a single layer of the superconductor material with a thickness equal to the collective thickness.

    摘要翻译: 本文公开了形成超导体的方法,包括以下步骤:提供衬底并将衬底暴露于第一气氛,包括前体以形成第一外延层段。 然后将第一层段暴露于第二气氛,包括形成第二外延层段的前体,并且将第二层段暴露于包含前体的第三气氛以形成第三外延层段。 第一和第三层段中的每一个均由超导体材料形成,第二层段由不同于第一和第三层段的材料形成,并且第一,第二和第三层段具有总体厚度,第三层 其外表面的粗糙度小于具有等于集体厚度的厚度的超导体材料的单层的粗糙度。