公开(公告)号：US06563227B1

公开(公告)日：2003-05-13

申请号：US10228789

申请日：2002-08-27

申请人： Richard J. Strnad

发明人： Richard J. Strnad

IPC分类号： H01L2338

CPC分类号： G05D23/1919 ,  H01L23/38 ,  H01L2924/0002 ,  H01L2924/00

摘要： Application of a potential difference across a doped region formed on an integrated circuit allows management of thermal energy directly on the chip surface. Individual temperature control cells are formed by ion implanting N- and P-type dopant into adjacent regions, and then forming a metal bridge across the similarly positioned ends. Placing a potential drop across metal contacts of the cell changes the temperature of the contacts relative to that of the electrically conducting bridge. Fabrication of arrays of temperature control cells of various shapes and sizes permits extremely precise heating and cooling of specific regions of the integrated circuit. Management of thermal energy on the IC in accordance with the present invention may be enhanced by forming arrays of temperature control cells possessing multiple tiers.

摘要翻译： 在形成在集成电路上的掺杂区域上施加电位差允许直接在芯片表面上管理热能。 通过将N型和P型掺杂剂离子注入到相邻区域中形成单独的温度控制电池，然后在相似位置的端部形成金属桥。 在电池的金属触点之间放置电位降使接触件的温度相对于导电桥的温度变化。 各种形状和尺寸的温度控制电池阵列的制造允许对集成电路的特定区域进行非常精确的加热和冷却。 可以通过形成具有多层的温度控制单元的阵列来增强根据本发明的IC上的热能的管理。

公开(公告)号：US06310383B1

公开(公告)日：2001-10-30

申请号：US09269199

申请日：1999-03-30

申请人： Shigeru Watanabe ,  Yumiko Sakamaki

发明人： Shigeru Watanabe ,  Yumiko Sakamaki

IPC分类号： H01L2338

CPC分类号： H01L35/32 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of n-type bar-shaped devices (51) consisting of an n-type thermoelectric semiconductor and a plurality of p-type bar-shaped devices (52) consisting of a p-type thermoelectric semiconductor are regularly disposed or fixed through an insulating layer (50) to form a thermoelectric device block (53). End portions of the n-type bar shaped device (51) and the p-type bar-shaped device (52) are connected with an interconnection conductor (58a) on an upper surface (53a) and a lower surface (53b), which will be interconnecting end faces of the thermoelectric device block (53), to form a plurality of thermocouples connected in series. In addition, a pair of terminal conductors (58b, 58b) which is electrically connected with bar-shaped devices (51a, 52a) at least on one end portion and the other end portion of the n-type and p-type bar-shaped devices (51, 52) connected in series is formed on end face (53c) excluding the upper surface (53a) and the lower surface (53b) which will be an interconnecting end face of the thermoelectric device block (53), and a lead wire is connected to the terminal conductors (58b, 58b).

摘要翻译： 由n型热电半导体和由p型热电半导体组成的多个p型棒状器件（52）构成的多个n型棒状器件（51）通过 绝缘层（50）以形成热电器件块（53）。 n型棒状器件（51）和p型棒状器件（52）的端部与上表面（53a）和下表面（53b）上的互连导体（58a）连接， 将热电装置块（53）的相互连接的端面形成多个串联连接的热电偶。 另外，一对端子导体（58b，58b）与棒状器件（51a，52a）的至少一个端部电连接，另一端部与n型和p型棒状电连接 串联连接的器件（51,52）形成在不包括作为热电元件块（53）的互连端面的上表面（53a）和下表面（53b）的端面（53c）上，引线 导线连接到端子导体（58b，58b）。

公开(公告)号：US06833609B1

公开(公告)日：2004-12-21

申请号：US10354772

申请日：2003-01-30

申请人： James M. Fusaro ,  Robert F. Darveaux ,  Pablo Rodriguez

发明人： James M. Fusaro ,  Robert F. Darveaux ,  Pablo Rodriguez

IPC分类号： H01L2338

CPC分类号： H01L24/32 ,  H01L23/3121 ,  H01L23/4985 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Integrated circuit device packages and substrates for making the packages are disclosed. One embodiment of a substrate includes a planar sheet of polyimide having a first surface, an opposite second surface, and apertures between the first and second surfaces. A planar metal die pad and planar metal are attached to the second surface of the polyimide sheet. The apertures in the polyimide sheet are juxtaposed to the leads. A package made using the substrate includes an integrated circuit device mounted above the first surface of the polyimide sheet opposite the die pad. Bond wires are connected between the integrated circuit device and the leads through the apertures in the polyimide sheet. An encapsulant material covers the first surface of the polyimide sheet, the integrated circuit device, the bond wires, and the apertures. The die pad and leads are exposed at an exterior surface of the package.

摘要翻译： 公开了用于制造封装的集成电路器件封装和衬底。 衬底的一个实施例包括具有第一表面，相对的第二表面以及第一和第二表面之间的孔的聚酰亚胺的平面片。 平面金属管芯焊盘和平面金属附接到聚酰亚胺片的第二表面。 聚酰亚胺片中的孔与引线并列。 使用该基板制成的封装包括集成电路装置，安装在与芯片衬垫相对的聚酰亚胺片的第一表面上方。 接合线通过聚酰亚胺片中的孔连接在集成电路器件和引线之间。 密封剂材料覆盖聚酰亚胺片的第一表面，集成电路器件，接合线和孔。 芯片焊盘和引线暴露在封装的外表面。

公开(公告)号：US06476508B1

公开(公告)日：2002-11-05

申请号：US09866976

申请日：2001-05-29

申请人： Richard J. Strnad

发明人： Richard J. Strnad

IPC分类号： H01L2338

CPC分类号： G05D23/1919 ,  H01L23/38 ,  H01L2924/0002 ,  H01L2924/00

摘要： Application of a potential difference across a doped region formed on an integrated circuit allows management of thermal energy directly on the chip surface. Individual temperature control cells are formed by ion implanting N- and P- type dopant into adjacent regions, and then forming a metal bridge across the similarly positioned ends. Placing a potential drop across metal contacts of the cell changes the temperature of the contacts relative to that of the electrically conducting bridge. Fabrication of arrays of temperature control cells of various shapes and sizes permits extremely precise heating and cooling of specific regions of the integrated circuit. Management of thermal energy on the IC in accordance with the present invention may be enhanced by forming arrays of temperature control cells possessing multiple tiers.

摘要翻译： 在形成在集成电路上的掺杂区域上施加电位差允许直接在芯片表面上管理热能。 通过将N型和P-型掺杂剂离子注入到相邻区域中形成单独的温度控制电池，然后在相似位置的端部形成金属桥。 在电池的金属触点之间放置电位降使接触件的温度相对于导电桥的温度变化。 各种形状和尺寸的温度控制电池阵列的制造允许对集成电路的特定区域进行非常精确的加热和冷却。 可以通过形成具有多层的温度控制单元的阵列来增强根据本发明的IC上的热能的管理。

公开(公告)号：US06728904B2

公开(公告)日：2004-04-27

申请号：US10370518

申请日：2003-02-24

申请人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

发明人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

IPC分类号： H01L2338

CPC分类号： H01L24/49 ,  G11C5/04 ,  G11C5/06 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5386 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.

摘要翻译： 一种具有布线基板，至少两个半导体芯片和总线的电子电路封装。 通过总线连接的所有半导体芯片都是裸线封装在布线基板上，并且半导体芯片和布线基板通过在半导体芯片上形成的引线键合焊盘和布线基板之间的布线接合来连接。 布线基板可以是多层基板。 优选地，在多层布线基板的表面上形成绝缘层和形成在绝缘层的表面上的管芯接合接地，以便在芯片接合地下使用多层布线基板的一部分作为布线 或通孔区域，并且在芯片接合地上形成至少一个半导体芯片。 总线优选地包括两条数据总线，与一条数据总线连接的半导体芯片形成在布线基板的一侧，并且在另一条数据总线上连接的半导体芯片形成在布线基板的另一侧。

公开(公告)号：US06404042B1

公开(公告)日：2002-06-11

申请号：US09472143

申请日：1999-12-27

申请人： Minoru Sone ,  Akira Tanioka ,  Motoyasu Morinaga ,  Hideo Furuyama

发明人： Minoru Sone ,  Akira Tanioka ,  Motoyasu Morinaga ,  Hideo Furuyama

IPC分类号： H01L2338

CPC分类号： H01S5/02284 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/02216 ,  H01S5/02248 ,  H01S5/02415 ,  H01S5/0683 ,  Y10S257/93 ,  H01L2924/00014 ,  H01L2924/00

摘要： A chip mount structure called “subcarrier” and semiconductor device capable of efficiently retaining the temperature of a semiconductor element at a constant level by a Peltier cooler without degrading the signal transmission characteristics of a module even when the atmospheric environment for use in the module changes in outside air temperature are provided. The subcarrier includes an element support unit that is high in thermal conductivity and also an element wiring unit of low thermal conductivity. Increasing the thermal conductivity of element support unit makes it possible to provide superior heat conduction between the semiconductor element and Peltier cooler whereas decreasing the element wiring unit's thermal conductivity enables elimination of radiation and absorption or exchange of heat from the top and side surfaces thereof, which in turn leads to an ability to greatly suppress or minimize the thermal load relative to the Peltier cooler.

摘要翻译： 一种称为“副载波”的芯片安装结构和能够通过珀尔帖冷却器有效地将半导体元件的温度保持在恒定水平的芯片安装结构，而不会降低模块的信号传输特性，即使当模块中使用的大气环境发生变化时 提供室外空气温度。 副载波包括导热性高的元件支撑单元和低导热性的元件布线单元。 提高元件支撑单元的热导率使得可以在半导体元件和珀耳帖冷却器之间提供优异的热传导，而减少元件布线单元的导热性能够消除辐射和从其顶表面和侧表面吸收或交换热量， 这又导致相对于珀耳帖冷却器大大抑制或最小化热负载的能力。