公开(公告)号：US20230139346A1

公开(公告)日：2023-05-04

申请号：US17549685

申请日：2021-12-13

申请人： Intel Corporation

发明人： Liu LIU ,  Junchao DING ,  Yingming LIU ,  Jong Sun SEL ,  Yixin MA ,  Jinwoo LEE ,  Xi LIN

IPC分类号： G11C16/04 ,  G11C8/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

摘要： An embodiment of an apparatus may include a substrate, a memory array of vertical 3D NAND strings formed in the substrate, a staircase region formed in the substrate, a polysilicon wordline extended horizontally into the staircase region, a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline, and a punch stop layer disposed between the wordline contact and the polysilicon wordline. Other embodiments are disclosed and claimed.

公开(公告)号：US11641734B2

公开(公告)日：2023-05-02

申请号：US17659493

申请日：2022-04-18

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Szu-Yao Chang

IPC分类号： G11C8/14 ,  G11C11/402 ,  H01L49/02

摘要： A method of forming a semiconductor structure includes forming a capacitor on a substrate. A recess is formed in the capacitor. A drain region is formed in the recess. A word line is formed on the drain region. A gate structure is formed on the drain region, and the gate structure is electrically connected to the word line. A first bit line is formed on the gate structure, such that the first bit line servers as a source region.

公开(公告)号：US20230066312A1

公开(公告)日：2023-03-02

申请号：US17553772

申请日：2021-12-16

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Hongbin Zhu ,  Wei Liu ,  Yanhong Wang

IPC分类号： H01L27/11526 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/423 ,  G11C7/18 ,  G11C8/14

摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells, and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with a plurality of sides of the semiconductor body. One end of the semiconductor body coupled to the storage unit is flush with the gate structure. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

公开(公告)号：US20230030836A1

公开(公告)日：2023-02-02

申请号：US17813147

申请日：2022-07-18

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Guifen YANG ,  SUNGSOO CHI

IPC分类号： G11C8/08 ,  G11C8/14 ,  H01L27/02

摘要： A word line driver circuit may at least include multiple word line drivers, each of which including a PMOS transistor and at least one NMOS transistor. The multiple word line drivers include multiple PMOS transistors and multiple NMOS transistors. The multiple PMOS transistors are arranged side by side, and in an arrangement direction of the multiple PMOS transistors, a part of the multiple NMOS transistors are located on a side of the multiple PMOS transistors, and another part of the NMOS transistors are located on another side of the multiple PMOS transistors.

公开(公告)号：US11563005B2

公开(公告)日：2023-01-24

申请号：US16930398

申请日：2020-07-16

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Minsu Lee ,  Kiseok Lee ,  Minwoo Song ,  Hyun-Sil Oh ,  Min Hee Cho

IPC分类号： H01L27/108 ,  G11C8/14 ,  G11C7/18

摘要： A three-dimensional semiconductor device includes a first channel pattern on and spaced apart from a substrate, the first channel pattern having a first end and a second end that are spaced apart from each other in a first direction parallel to a top surface of the substrate, and a first sidewall and a second sidewall connecting between the first end and the second end, the first and second sidewalls being spaced apart from each other in a second direction parallel to the top surface of the substrate, the second direction intersecting the first direction, a bit line in contact with the first end of the first channel pattern, the bit line extending in a third direction perpendicular to the top surface of the substrate, and a first gate electrode adjacent to the first sidewall of the first channel pattern.

公开(公告)号：US20230018727A1

公开(公告)日：2023-01-19

申请号：US17933933

申请日：2022-09-21

申请人： XENERGIC AB

发明人： Babak Mohammadi ,  Joachim Neves Rodrigues

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C7/12 ,  G11C11/418 ,  G11C8/10 ,  G11C8/14

摘要： The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.

公开(公告)号：US11557604B2

公开(公告)日：2023-01-17

申请号：US17025120

申请日：2020-09-18

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Seongyeon Woo ,  Sangjun Hong ,  Jinsoo Lim ,  Jisung Cheon

IPC分类号： H01L27/11582 ,  H01L27/11565 ,  G11C8/14 ,  H01L27/11556 ,  H01L27/11519

摘要： A semiconductor device includes: a first gate stack including a plurality of first gate electrodes; a second gate stack arranged on the first gate stack and including a plurality of second gate electrodes; and a plurality of channel structures arranged in a plurality of channel holes penetrating the first gate stack and the second gate stack. Each of the channel holes includes a first channel hole portion penetrating the first gate stack and a second channel hole portion penetrating the second gate stack, and a ratio of a second width in the second direction to a first width in the first direction of an upper end of the first channel hole portion is less than a ratio of a fourth width in the second direction to a third width in the first direction of an upper end of the second channel hole portion.

公开(公告)号：US11545500B2

公开(公告)日：2023-01-03

申请号：US17157489

申请日：2021-01-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Bo-Feng Young ,  Sai-Hooi Yeong ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Yu-Ming Lin

IPC分类号： H01L27/11551 ,  H01L27/11519 ,  G11C8/14 ,  G11C7/18

摘要： In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer.

公开(公告)号：US11538829B2

公开(公告)日：2022-12-27

申请号：US17004048

申请日：2020-08-27

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Erh-Kun Lai

IPC分类号： G11C8/14 ,  H01L27/1157 ,  H01L27/11582 ,  G11C7/18 ,  G11C16/04

摘要： A memory device and a manufacturing for the same are provided. The memory device comprises a channel line, word lines, a first switch, and a second switch. Memory cells for a memory string are defined at intersections between the channel line and the word lines. The first switch is electrically connected with the channel line. The second switch is electrically connected with the channel line. The first switch is electrically connected between the second switch and the memory cells.

公开(公告)号：US20220406351A1

公开(公告)日：2022-12-22

申请号：US17643499

申请日：2021-12-09

申请人： KIOXIA CORPORATION

发明人： Noriyasu KUMAZAKI

IPC分类号： G11C8/14 ,  G11C8/08

摘要： A semiconductor memory device includes memory cell arrays including a first memory cell and a first word line connected to the first memory cell, a first wiring electrically connected to the first word lines corresponding to the memory cell arrays, a driver circuit electrically connected to the first wiring, second wirings electrically connected to the first wiring via the driver circuit, a voltage generation circuit including output terminals disposed corresponding to the second wirings, and first circuits disposed corresponding to the memory cell arrays. The voltage generation circuit is electrically connected to the first word lines via a first current path including the second wirings, the driver circuit, and the first wiring. The voltage generation circuit is electrically connected to the first word lines via a second current path including the second wirings and the first circuits and without including the driver circuit.