FINFET FABRICATION METHODS
    3.
    发明申请

    公开(公告)号:US20220208986A1

    公开(公告)日:2022-06-30

    申请号:US17654807

    申请日:2022-03-14

    摘要: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

    VERTICAL TRANSISTOR INCLUDING SYMMETRICAL SOURCE/DRAIN EXTENSION JUNCTIONS

    公开(公告)号:US20210265488A1

    公开(公告)日:2021-08-26

    申请号:US16797097

    申请日:2020-02-21

    摘要: A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.

    A METHOD FOR SELECTIVE INCORPORATION OF DOPANT ATOMS IN A SEMICONDUCTIVE SURFACE

    公开(公告)号:US20210242022A1

    公开(公告)日:2021-08-05

    申请号:US17051739

    申请日:2019-05-02

    IPC分类号: H01L21/223

    摘要: The present disclosure is directed to a methodology for embedding a deterministic number of dopant atoms in a surface portion of a group IV semiconductor lattice. The methodology comprises the steps of: forming one or more lithographic sites on the surface portion; dosing, at a temperature below 100 K, the surface portion using a gas with molecules comprising the dopant atom and hydrogen atoms in a manner such that, a portion of the molecules bonds to the surface portion; and incorporating one or more dopant atoms in a respective lithographic site by transferring an amount of energy to the dopant atoms. The number of dopant atoms incorporated in a lithographic site is deterministic and related to the size of the lithographic site.