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公开(公告)号：US11640946B2
公开(公告)日：2023-05-02
申请号：US17466941
申请日：2021-09-03
发明人： Denis Farison , Romain Coffy , Jean-Michel Riviere
IPC分类号： H01L23/52 , H01L23/00 , H01L21/56 , H01L23/528 , H01L25/065 , H04L9/00
摘要： A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.
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公开(公告)号：US11640928B2
公开(公告)日：2023-05-02
申请号：US17412423
申请日：2021-08-26
IPC分类号： H01L21/48 , H01L23/48 , H01L23/52 , H01L23/367 , H01L23/522 , H01L23/373
摘要： Various embodiments of the present disclosure are directed towards a semiconductor structure including a device layer having a front-side surface opposite a back-side surface. A first heat dispersion layer is disposed along the back-side surface of the device layer. A second heat dispersion layer underlies the front-side surface of the device layer. The second heat dispersion layer has a thermal conductivity lower than a thermal conductivity of the first heat dispersion layer.
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公开(公告)号：US11621227B2
公开(公告)日：2023-04-04
申请号：US17540141
申请日：2021-12-01
申请人： Intel Corporation
发明人： Kemal Aygun , Zhiguo Qian , Jianyong Xie
IPC分类号： H01L23/52 , H01L21/00 , H01L23/538 , H01L21/48 , H01L23/48 , H01L23/498 , H01L23/31 , H01L23/00 , H01L23/522 , H01L23/532
摘要： Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.
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公开(公告)号：US11616013B2
公开(公告)日：2023-03-28
申请号：US16900567
申请日：2020-06-12
发明人： Hung Hsun Lin , Che-Chih Hsu , Wen-Chu Huang , Chinyu Su , Yen-Yu Chen , Wei-Chun Hua , Wen Han Hung
IPC分类号： H01L23/52 , H01L23/522 , H01L23/66 , H01L49/02 , H01L21/768 , H01L23/64
摘要： A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
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公开(公告)号：US11587827B2
公开(公告)日：2023-02-21
申请号：US17567762
申请日：2022-01-03
申请人： Intel Corporation
发明人： Sean King , Hui Jae Yoo , Sreenivas Kosaraju , Timothy Glassman
IPC分类号： H01L21/76 , H01L23/52 , H01L21/02 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/00
摘要： Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.
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公开(公告)号：US11574914B2
公开(公告)日：2023-02-07
申请号：US17380603
申请日：2021-07-20
发明人： Jar-Ming Ho
IPC分类号： H01L27/108 , H01L23/52 , H01L23/522
摘要： The present application discloses a method for fabricating a semiconductor device. The method includes: providing a substrate including a plurality of first regions and second regions; forming a plurality of bit line contacts over the first regions of the substrate; forming a plurality of bit lines respectively over the plurality of bit line contacts; forming a plurality of capacitor contacts respectively over the second regions of the substrate; forming a plurality of capacitor plugs respectively over the plurality of capacitor contacts; forming a plurality of first spacers respectively over a plurality of protruding portions of the plurality of capacitor plugs, wherein a width of the first spacer is larger than a width of the capacitor plug; and forming a plurality of capacitor structures over the plurality of first spacers; wherein at least one of the plurality of bit lines is an undulating stripe extending between two adjacent capacitor contacts.
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公开(公告)号：US11574889B2
公开(公告)日：2023-02-07
申请号：US13909133
申请日：2013-06-04
发明人： Ottmar Geitner , Wolfram Hable , Andreas Grassmann , Frank Winter , Christian Neugirg , Ivan Nikitin
IPC分类号： H01L23/48 , H01L23/52 , H01L23/00 , H01L23/495 , H01L23/373 , H01L23/31 , H01L25/00 , H01L23/433
摘要： A method of manufacturing a power module comprising two substrates is provided, wherein the method comprises disposing a compensation layer of a first thickness above a first substrate; disposing a second substrate above the compensation layer; and reducing the thickness of the compensation layer from the first thickness to a second thickness after the second substrate is disposed on the compensation layer.
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公开(公告)号：US11574867B2
公开(公告)日：2023-02-07
申请号：US17104078
申请日：2020-11-25
发明人： Ephrem G. Gebreselasie , Vibhor Jain , Yves T. Ngu , Johnatan A. Kantarovsky , Alain F. Loiseau
IPC分类号： H01L23/52 , H01L23/525 , H01L21/8249 , H01L21/02 , H01L27/07 , H01L23/62 , H01L27/115 , H01L27/112 , H01L27/02
摘要： An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.
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公开(公告)号：US11569202B2
公开(公告)日：2023-01-31
申请号：US17396773
申请日：2021-08-09
发明人： Tin-Hao Kuo , Chen-Hua Yu , Chung-Shi Liu , Hao-Yi Tsai , Yu-Chia Lai , Po-Yuan Teng
IPC分类号： H01L23/52 , H01L25/065 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/538 , H01L23/00 , H01L23/31 , H05K1/02 , H01L25/00
摘要： A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.
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公开(公告)号：US11569185B2
公开(公告)日：2023-01-31
申请号：US17074175
申请日：2020-10-19
摘要： A method for forming a multilayer conductive structure includes forming a first conductive portion; forming a second conductive portion containing ruthenium (Ru) therein on the first conductive portion; forming a third conductive portion on the second conductive portion; and performing a silicidation process on the second conductive portion.
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