公开(公告)号：US20230138899A1

公开(公告)日：2023-05-04

申请号：US17827805

申请日：2022-05-30

申请人： GlobalWafers Co., Ltd.

发明人： Tzu-Yao Lin ,  Jia-Zhe Liu ,  Ying-Ru Shih

IPC分类号： H01L29/15 ,  H01L29/267

摘要： A semiconductor epitaxy structure includes a silicon carbide substrate, a nucleation layer, a gallium nitride buffer layer, and a stacked structure. The nucleation layer is formed on the silicon carbide substrate, the gallium nitride buffer layer is disposed on the nucleation layer, and the stacked structure is formed between the nucleation layer and the gallium nitride buffer layer. The stacked structure includes: a plurality of silicon nitride (SiNx) layers and a plurality of aluminum gallium nitride (AlxGa1-xN) layers alternately stacked, wherein the first layer of the plurality of silicon nitride layers is in direct contact with the nucleation layer.

公开(公告)号：US11605716B2

公开(公告)日：2023-03-14

申请号：US17095195

申请日：2020-11-11

申请人： CoorsTek KK

发明人： Hiroshi Oishi ,  Jun Komiyama ,  Yoshihisa Abe ,  Kenichi Eriguchi

IPC分类号： H01L29/207 ,  H01L29/20 ,  H01L21/02 ,  H01L29/06 ,  H01L29/778 ,  H01L29/267

摘要： The present invention provides a nitride semiconductor substrate suitable for a high frequency device. The nitride semiconductor substrate has a substrate, a buffer layer made of group 13 nitride semiconductors, and an active layer made of group 13 nitride semiconductors in this order, wherein the substrate is composed of a first substrate made of polycrystalline aluminum nitride, and a second substrate made of Si single crystal having a specific resistance of 100 Ω·cm or more, formed on the first substrate, the average particle size of AlN constituting the first substrate is 3 to 9 μm, and preferably, the second substrate grown by the MCZ method has an oxygen concentration of 1E+18 to 9E+18 atoms/cm3 and a specific resistance of 100 to 1000 Ω·cm.

公开(公告)号：US20230047356A1

公开(公告)日：2023-02-16

申请号：US17401323

申请日：2021-08-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Oreste Madia ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal

IPC分类号： H01L29/267 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

摘要： A semiconductor device is provided. The semiconductor device includes a gate layer, a semiconductor layer and a ferroelectric layer disposed between the gate layer and the semiconductor layer. The semiconductor layer includes a first material containing a Group III element, a rare-earth element and a Group VI element, the ferroelectric layer includes a second material containing a Group III element, a rare-earth element and a Group V element and the gate layer includes a third material containing a Group III element and a rare-earth element. A method of fabricating a semiconductor device is also provided.

公开(公告)号：US11581313B2

公开(公告)日：2023-02-14

申请号：US16283301

申请日：2019-02-22

申请人： Intel Corporation

发明人： Sansaptak Dasgupta ,  Johann Christian Rode ,  Han Wui Then ,  Marko Radosavljevic ,  Paul B. Fischer ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Sandrine Charue-Bakker ,  Walid M. Hafez

IPC分类号： H01L27/092 ,  H01L29/26 ,  H01L21/8238 ,  H01L21/8258 ,  H01L29/267

摘要： Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor regrowth. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by depositing a III-N material, forming an opening in the III-N material, and epitaxially growing within the opening a semiconductor material other than the III-N material. Since the III-N material may serve as a foundation for forming III-N transistors, while the non-III-N material may serve as a foundation for forming non-III-N transistors, such an approach advantageously enables implementation of both types of transistors on a single support structure. Proposed integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.

公开(公告)号：US11569386B2

公开(公告)日：2023-01-31

申请号：US17135316

申请日：2020-12-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/167 ,  H01L23/535 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/088 ,  H01L29/417

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure extended above a substrate, and a first source/drain structure formed over the first fin structure. The first source/drain structure is made of an N-type conductivity material. The semiconductor device structure also includes a second source/drain structure formed over the second fin structure, and the second source/drain structure is made of an P-type conductivity material. The semiconductor device structure also includes a cap layer formed over the first source/drain structure, wherein the cap layer is made of P-type conductivity material.

公开(公告)号：US11569378B2

公开(公告)日：2023-01-31

申请号：US17130969

申请日：2020-12-22

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Christopher Boguslaw Kocon

IPC分类号： H01L29/78 ,  H01L29/267 ,  H01L29/66 ,  H01L29/40

摘要： A semiconductor device includes a first semiconductor structure. The first semiconductor structure includes a first semiconductor material having a band-gap. The first semiconductor structure has a first surface. An insulating layer has first and second opposing surfaces. The first surface of the insulating layer is on the first surface of the first semiconductor structure. A second semiconductor structure is on the second surface of the insulating layer and includes a second semiconductor material having a band-gap that is smaller than the band-gap of the first semiconductor material. A floating electrode couples the first semiconductor structure to the second semiconductor structure.

公开(公告)号：US11563118B2

公开(公告)日：2023-01-24

申请号：US16659391

申请日：2019-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Zhiqiang Wu ,  Carlos H. Diaz

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L21/324 ,  H01L27/11 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66

摘要： The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer.

公开(公告)号：US11538938B2

公开(公告)日：2022-12-27

申请号：US16725501

申请日：2019-12-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Che-Wei Yang ,  Hao-Hsiung Lin ,  Samuel C. Pan

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/267 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/06 ,  H01L29/36

摘要： A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.

公开(公告)号：US11521957B1

公开(公告)日：2022-12-06

申请号：US17370597

申请日：2021-07-08

申请人： RFHIC Corporation

发明人： Won Sang Lee

IPC分类号： H01L23/00 ,  H01L25/18 ,  H01L29/778 ,  H01L29/16 ,  H01L23/48 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/78 ,  H01L29/267

摘要： In one embodiment, a semiconductor device includes a first substrate with a transistor formed in a first active are, a first bonding pad electrically connected to the transistor and a first metal pad surrounding the first active area. A second substrate of a type that is different from the first substrate includes a passive circuit element in a second active area on a front surface, a second bonding pad electrically connected to the passive circuit element, a second metal pad surrounding the second active area, and a mounting pad on a back surface of the second substrate with a through-via electrically connecting the second bonding pad to the mounting pad. A first interconnection extends from the first bonding pad to the second bonding pad, and a second interconnection extends from the first metal pad to the second metal pad and surrounds the region through which the first interconnection extends.

公开(公告)号：US20220384276A1

公开(公告)日：2022-12-01

申请号：US17876083

申请日：2022-07-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Han Chen ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L21/8238 ,  H01L29/165 ,  H01L29/267 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08

摘要： In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having an upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.