公开(公告)号：US20200052119A1

公开(公告)日：2020-02-13

申请号：US16659391

申请日：2019-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Zhiqiang Wu ,  Carlos H. Diaz

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/11 ,  H01L21/324 ,  H01L29/51 ,  H01L29/49 ,  H01L29/267 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L27/092

摘要： The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer.

公开(公告)号：US10163905B2

公开(公告)日：2018-12-25

申请号：US15700377

申请日：2017-09-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Chih-Sheng Chang ,  Zhiqiang Wu

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L29/16 ,  H01L29/165 ,  H01L29/161 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/311 ,  H01L29/78 ,  H01L29/167 ,  H01L29/06

摘要： The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion.

公开(公告)号：US09941406B2

公开(公告)日：2018-04-10

申请号：US14527660

申请日：2014-10-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Zhiqiang Wu

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

摘要： A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.

公开(公告)号：US20180076097A1

公开(公告)日：2018-03-15

申请号：US15805892

申请日：2017-11-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Zhiqiang Wu

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L21/823821 ,  H01L21/02233 ,  H01L21/02532 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

摘要： Various methods are disclosed herein for fabricating non-planar circuit devices having strain-producing features. An exemplary method includes forming a fin structure that includes a first portion that includes a first semiconductor material and a second portion that includes a second semiconductor material that is different than the first semiconductor material. The method further includes forming a masking layer over a source region and a drain region of the fin structure, forming a strain-producing feature over the first portion of the fin structure in a channel region, removing the masking layer and forming an isolation feature over the strain-producing feature, forming an epitaxial feature over the second portion of the fin structure in the source region and the drain region, and performing a gate replacement process to form a gate structure over the second portion of the fin structure in the channel region.

公开(公告)号：US09837321B2

公开(公告)日：2017-12-05

申请号：US15088278

申请日：2016-04-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Zhiqiang Wu

IPC分类号： H01L21/8238 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/762

CPC分类号： H01L21/823821 ,  H01L21/02233 ,  H01L21/02532 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

摘要： A nonplanar circuit device having a strain-producing structure disposed under the channel region is provided. In an exemplary embodiment, the integrated circuit device includes a substrate with a first fin structure and a second fin structure disposed on the substrate. An isolation feature trench is defined between the first fin structure and the second fin structure. The circuit device also includes a strain feature disposed on a horizontal surface of the substrate within the isolation feature trench. The strain feature may be configured to produce a strain on a channel region of a transistor formed on the first fin structure. The circuit device also includes a fill dielectric disposed on the strain feature within the isolation feature trench. In some such embodiments, the strain feature is further disposed on a vertical surface of the first fin structure and on a vertical surface of the second fin structure.

公开(公告)号：US20170301588A1

公开(公告)日：2017-10-19

申请号：US15637088

申请日：2017-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Chih-Sheng Chang ,  Zhiqiang Wu

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L29/78 ,  H01L29/772 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L27/12 ,  H01L27/092 ,  H01L27/088 ,  H01L21/84 ,  H01L29/165

CPC分类号： H01L21/823821 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7831 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7855

摘要： The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner.

公开(公告)号：US09548362B2

公开(公告)日：2017-01-17

申请号：US14555128

申请日：2014-11-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Zhiqiang Wu

IPC分类号： H01L21/00 ,  H01L29/10 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L29/1083 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66545

摘要： An embodiment semiconductor device includes a fin extending upwards from a semiconductor substrate. The fin includes an anti-punch through (APT) layer having APT dopants and a channel region over the APT layer. The channel region is substantially free of APT dopants. The semiconductor device further includes a conductive gate stack on a sidewall and a top surface of the channel region.

摘要翻译： 实施例半导体器件包括从半导体衬底向上延伸的鳍片。 翅片包括具有APT掺杂剂的抗穿透（APT）层和APT层上的沟道区。 通道区域基本上不含APT掺杂剂。 半导体器件还包括在沟道区域的侧壁和顶表面上的导电栅极堆叠。

公开(公告)号：US09543209B2

公开(公告)日：2017-01-10

申请号：US14864037

申请日：2015-09-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ka-Hing Fung

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L21/84 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7853

摘要： A method includes forming a first semiconductor fin, and oxidizing surface portions of the first semiconductor fin to form a first oxide layer. The first oxide layer includes a top portion overlapping the first semiconductor fin and sidewall portions on sidewalls of the first semiconductor fin. The top portion of the first oxide layer is then removed, wherein the sidewall portions of the first oxide layer remains after the removing. The top portion of the first semiconductor fin is removed to form a recess between the sidewall portions of the first oxide layer. An epitaxy is performed to grow a semiconductor region in the recess.

摘要翻译： 一种方法包括形成第一半导体鳍片，以及氧化第一半导体鳍片的表面部分以形成第一氧化物层。 第一氧化物层包括与第一半导体鳍片重叠的顶部部分和在第一半导体鳍片的侧壁上的侧壁部分。 然后去除第一氧化物层的顶部，其中第一氧化物层的侧壁部分在去除之后保留。 去除第一半导体翅片的顶部以在第一氧化物层的侧壁部分之间形成凹陷。 进行外延以在凹部中生长半导体区域。

公开(公告)号：US09362404B2

公开(公告)日：2016-06-07

申请号：US14186910

申请日：2014-02-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hung-Kai Chen ,  Tsung-Hung Lee ,  Han-Pin Chung ,  Shih-Syuan Huang ,  Chun-Fu Cheng ,  Chien-Tai Chan ,  Kuang-Yuan Hsu ,  Hsien-Chin Lin ,  Ka-Hing Fung

IPC分类号： H01L29/00 ,  H01L29/78 ,  H01L29/06 ,  H01L21/225

CPC分类号： H01L21/2251 ,  H01L21/2255 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0657 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7851

摘要： First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.

公开(公告)号：US20160049338A1

公开(公告)日：2016-02-18

申请号：US14924422

申请日：2015-10-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Chih-Sheng Chang ,  Zhiqiang Wu

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02

CPC分类号： H01L21/823821 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7831 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7855

摘要： The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner.

摘要翻译： 本公开提供了鳍状场效应晶体管（FinFET）器件的实施例。 该器件包括具有第一栅极区域的衬底，在第一栅极区域中的衬底上的第一鳍状结构。 第一鳍片结构包括上半导体材料构件，下半导体材料构件，被氧化物特征包围，并且衬垫围绕下半导体材料构件的氧化物特征包围，并向上延伸以围绕上部半导体的下部 材料成员。 该装置还包括横向靠近上半导体材料构件的上部的电介质层。 因此，上部半导体材料构件包括中间部分，其既不横向接近电介质层也不被衬垫缠绕。