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公开(公告)号：US20240179465A1
公开(公告)日：2024-05-30
申请号：US18060279
申请日：2022-11-30
CPC分类号： H04R5/04 , H03F1/3205 , H03F3/185 , H04R2420/07 , H04R2420/09
摘要： A wireless device may include a plug that is shared by high speed data, analog audio signals, and power. Switches may be included on wires between the plug and the circuits that provide the high-speed data, analog audio signals and power to isolate those circuits from overvoltage conditions. Linearizer circuits may be included to provide gate driving signals to the switches, e.g., during transmission of analog audio signals. The linearizer circuits may include digital-to-analog converters to apply a gain factor to analog audio signals.
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公开(公告)号：US20240063762A1
公开(公告)日：2024-02-22
申请号：US18496448
申请日：2023-10-27
申请人： Nevin STEINBERG , Andrew FUNK , Jason CRYSTAL
发明人： Nevin STEINBERG , Andrew FUNK , Jason CRYSTAL
CPC分类号： H03F3/185 , H04R29/007 , H03G9/005 , H03G3/32
摘要： An exemplary audio enhancement system substantially eliminates latency by returning audio input signals in amplified form directly in the analog domain to the source, thereby reducing signal degradation and removing redundancy from digital and analog audio transmission and processing architectures.
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公开(公告)号：US20230412134A1
公开(公告)日：2023-12-21
申请号：US18185301
申请日：2023-03-16
申请人： QSC, LLC
发明人： Anders Lind , Matthew Skogmo
CPC分类号： H03F3/68 , H03F3/183 , H03F3/2173 , H04R3/00 , H03F1/0277 , H03F3/185 , H03F2200/321 , H03F2200/03
摘要： An amplifier having one or more channels where each channel includes a two half bridges (a master and slave sub-channel). The sub-channels can be connected either in parallel or in a full-bridge configuration via internal switches that route signals to a pair of speaker jacks. One switch in the amplifier has a first position that selectively connects the outputs of the master and slave sub-channel to the same input of the speaker load so that the two sub-channels will drive the speaker load in parallel and a second position where the output of the slave sub-channel is connected to another input of the speaker load so that the master sub-channel and the slave sub-channel will drive the speaker load in a Full-bridge configuration. A second switch has a first position that connects a second input of the speaker load to ground or reference potential of the sub-channels when the speaker load is to be driven in parallel and a second position that is a No-connect position that is used when the speaker load is driven in the Full-bridge configuration and a ground potential is not to be connected to the speaker.
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公开(公告)号：US20230336133A1
公开(公告)日：2023-10-19
申请号：US17720796
申请日：2022-04-14
发明人： John L. MELANSON
CPC分类号： H03F3/2171 , H03F3/185 , H03K7/08 , H03F2200/351 , H03F2200/03
摘要： A switched mode amplifier system may include a switched mode amplifier having an amplifier input coupled to an output of an analog integrator and an amplifier output, include a feedback network coupled between the amplifier output and an input of the analog integrator, include a loop filter configured to generate a digital loop filter output, include a quantizer configured to generate a pulse-width modulated representation of the digital loop filter output; and include a calibration system. The calibration system may be configured to force the input of the analog integrator to a fixed known input value, low-pass filter the pulse-width modulated representation of the digital loop filter output generated by the quantizer to generate a filtered quantizer output signal, determine an offset of the switched mode amplifier system based on the filtered quantizer output signal, and correct for the offset.
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公开(公告)号：US11777415B2
公开(公告)日：2023-10-03
申请号：US17240268
申请日：2021-04-26
CPC分类号： H02M3/33592 , H03F3/2173
摘要： An amplifier system may include at least one input source, a converter configured to provide voltage rails to an amplifier, the voltage rails including a first voltage rail and a second voltage rail, a MOSFET arranged at a secondary side of the system at the first voltage rail, a second MOSFET arranged at the first voltage rail, a third MOSFET arranged at the second voltage rail, a fourth MOSFET arranged at the second voltage rail; and, a first capacitor arranged at the first voltage rail and a second capacitor arranged at the second voltage rail, the first and forth MOSFETS are configured to operate simultaneously with one another and the second and third MOSFETs are configured to operate simultaneously with one another and opposite of the first and fourth MOSFETs so as to allow synchronous rectification so that the first and second capacitors reciprocally and mutually exclusively charge and discharge.
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公开(公告)号：US20230261617A1
公开(公告)日：2023-08-17
申请号：US18135060
申请日：2023-04-14
申请人： Logitech Europe S.A.
CPC分类号： H03F3/1855 , H04R1/04 , H04R1/2807 , H04R3/04 , H04R7/04 , H04R9/08 , H03F2200/03
摘要： A microphone system includes a microphone and a pre-amplification conditioning circuit configured within a housing and comprising a pair of matched JFETs configured in a differential pair with common-source configuration and, when biased, are operable to receive and amplify the differential microphone output signal. The microphone further includes a pair of BJTs configured as a complimentary feedback transistor pair with each of the pair of BJTs coupled in parallel to a corresponding one of the pair of matched JFETs, and a current sink coupled to the matched JFETs and corresponding emitter electrodes of the BJTs and operable to maintain a fixed total direct current through each of the matched JFETs and BJTs, which reduces the JFETs corresponding electrical load, reduces signal noise, and increases a maximum amplified microphone output signal level at the drains of the matched JFETs.
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公开(公告)号：US11658623B2
公开(公告)日：2023-05-23
申请号：US17378861
申请日：2021-07-19
发明人： John Paul Lesso , Toru Ido
CPC分类号： H03F3/2173 , H04R3/00 , H04R29/001 , H03F3/185 , H03F2200/03 , H03F2200/165 , H03F2200/168 , H03F2200/267 , H04R2499/11
摘要： The present disclosure relates to Class D amplifier circuitry comprising a mode controller configured to dynamically adjust an operational switching mode of the Class D amplifier over a range between a Class AD mode and a Class BD mode.
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公开(公告)号：US20230089860A1
公开(公告)日：2023-03-23
申请号：US17932827
申请日：2022-09-16
申请人： Paul R. Higgins
发明人： Paul R. Higgins
IPC分类号： H03F3/185
摘要： A musical instrument preamplifier includes a n-type JFET and a pnp current mirror connected to the drain side of the JFET. The pnp current mirror includes two pnp transistors. The current mirror is configured to control the current to independently set the operating point of the JFET and the output. An npn transistor is connected to one of the pnp transistors of the current mirror to form an inverted Sziklai pair. An auto-bias network is connected between the npn and pnp transistors that form the Sziklai pair.
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公开(公告)号：US20220376730A1
公开(公告)日：2022-11-24
申请号：US17323685
申请日：2021-05-18
摘要： An aspect includes an apparatus including a first amplifier; a first field effect transistor (FET) including a first source coupled to an output of the first amplifier, and a first drain for coupling to a first load; and a first gate drive circuit including an input coupled to the output of the first amplifier and an output coupled to a first gate of the first FET. Another aspect includes a method including amplifying a first audio signal using a first audio amplifier to generate a first voltage; generating a first gate voltage based on the first voltage; applying the first gate voltage to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and a first audio transducer; and applying the first voltage to a first source of the first FET.
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公开(公告)号：US11469753B1
公开(公告)日：2022-10-11
申请号：US17365201
申请日：2021-07-01
发明人： Hamed Sadati , Yu Tamura
摘要： A switching driver circuit may have an output stage having an output switch connected between a switching voltage node and an output node. A switch network may control a switching voltage at the switching voltage node so that in one mode the switching voltage node is coupled to a positive voltage and in another mode the switching voltage node is coupled to ground voltage via a first switching path of the switch network. The circuit may also include an n-well switching block operable to, when the first switching voltage node is coupled to a positive voltage, connect the n-well of the first output switch to the switching voltage node, and, when the first switching voltage node is coupled to the ground voltage, connect the n-well of the first output switch to a first ground which is separate to the first switching voltage node and independent of the first switching path.
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