公开(公告)号：US12230361B2

公开(公告)日：2025-02-18

申请号：US18346565

申请日：2023-07-03

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Mohamed H. Abu-Rahma ,  Jelam K. Parekh ,  Yildiz Sinangil ,  Mohammad Ghasemzadeh ,  Anthony Ghannoum ,  Chaminda N. Vidanagamachchi

IPC: G11C8/00 ,  G11C7/10 ,  G11C7/22 ,  H03M1/82

Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

公开(公告)号：US20240305311A1

公开(公告)日：2024-09-12

申请号：US18120097

申请日：2023-03-10

Applicant: Webasto Charging Systems, Inc.

Inventor： Peter Gabrielsson

IPC: H03M1/82 ,  H03M13/25

CPC classification number: H03M1/822 ,  H03M13/25

Abstract: Systems, devices, and methods for a high-voltage conversion circuit system comprising: an error detection and correction module configured to receive an analog input signal and a feedback signal and generate a correction signal; and an analog to pulse width modulation (PWM) module configured to receive the analog input signal and correction signal and generate a PWM output signal; where the generated PWM output signal is fed back to the error detection and correction module as said feedback signal.

公开(公告)号：US20240291501A1

公开(公告)日：2024-08-29

申请号：US18654911

申请日：2024-05-03

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John L. MELANSON ,  Lingli ZHANG ,  Paul M. ASTRACHAN ,  James KELTON

IPC: H03M1/82 ,  H03M1/18

CPC classification number: H03M1/822 ,  H03M1/183

Abstract: A digital-to-analog converter (DAC) may include an integrator, an input network, and control circuitry. The input network may include a plurality of parallel taps, each having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member is coupled between an input of the digital-to-analog converter and an input of the integrator. The control circuitry may be configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the DAC, such that the control circuitry enables, substantially contemporaneously, an even number of members at a time in order to increase the analog gain, with half of such enabled members in a first group and half of such enabled members in a second group.

公开(公告)号：US12068755B2

公开(公告)日：2024-08-20

申请号：US17944340

申请日：2022-09-14

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Shih-Hsiung Huang ,  Wei-Cian Hong ,  Sheng-Yen Shih

IPC: H03M1/80 ,  H03M1/56 ,  H03M1/74 ,  H03M1/82

CPC classification number: H03M1/804 ,  H03M1/56 ,  H03M1/742 ,  H03M1/825

Abstract: A digital slope analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, a detector circuit, and a control logic circuitry. The charge injection DAC circuit respectively samples input signals via first and second capacitors and generates a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal with the second signal to generate decision signals. The detector circuit generates a flag signal according to the decision signals. The control logic circuitry generates an enable signal according to the flag signal and generates a digital output when the comparator circuit detects a crossing point of the first and second signals. The charge injection DAC circuit gradually adjusts charges stored in the first and/or the second capacitor according to the enable signal until the crossing point is detected.

公开(公告)号：US20240113699A1

公开(公告)日：2024-04-04

申请号：US17957339

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Martin Langhammer

IPC: H03H17/06 ,  H03M1/82

CPC classification number: H03H17/0657 ,  H03M1/82

Abstract: Integrated circuit devices, methods, and circuitry for implementing and using a flexible circuit for real and complex filter operations are provided. An integrated circuit may include programmable logic circuitry and digital signal processor (DSP) blocks. The DSP blocks may be configurable to receive inputs from the programmable logic circuitry and may include first and second multiplier pairs. The first multiplier pair may include a first multiplier that may receive a first input and a second input and a second multiplier that may receive the second input and a third input of the inputs. The second multiplier pair may include a third multiplier that may receive the first input or a fourth input and a fifth input and a fourth multiplier that may receive the third input or a fifth input and a sixth input.

公开(公告)号：US20240088844A1

公开(公告)日：2024-03-14

申请号：US18243754

申请日：2023-09-08

Applicant: STMicroelectronics S.r.l.

Inventor： Edoardo BOTTI ,  Francesco STILGENBAUER ,  Piero MALCOVATI ,  Edoardo BONIZZONI ,  Matteo DE FERRARI

IPC: H03F3/217 ,  H03F1/02 ,  H03M1/82 ,  H03M3/00

CPC classification number: H03F3/2175 ,  H03F1/0255 ,  H03M1/822 ,  H03M3/424 ,  H03F2200/03

Abstract: Signal processing is applied to a digital audio input signal to provide an analog audio output signal using a switching converter circuit driven by a pulse-width-modulated (PWM) signal. The analog audio output signal is sensed to provide an analog feedback signal. The signal processing that is applied includes: converting the digital audio input signal to producing an analog replica; producing an analog error signal indicative of a difference between the analog replica of the digital input signal and the analog feedback signal; converting the analog error signal to produce a digital error signal; digitally filtering the digital error signal to produce a filtered digital error signal; and generating the PWM signal from the filtered digital error signal.

公开(公告)号：US20240069173A1

公开(公告)日：2024-02-29

申请号：US17898432

申请日：2022-08-29

Applicant: PixArt Imaging Inc.

Inventor： Yueh-Lin Chung ,  Tso-Sheng Tsai

IPC: G01S7/4865 ,  G01B11/22 ,  H03M1/80 ,  H03M1/82

CPC classification number: G01S7/4865 ,  G01B11/22 ,  H03M1/802 ,  H03M1/82

Abstract: An output stage circuit, comprising: a current source circuit; an output switch circuit, comprising at least one output switch, coupled to the current source circuit, wherein an output current flows through a target circuit when the output switch circuit is conducted; at least one bias capacitor, coupled to the current source circuit; and a bias switch circuit, configured to receive a bias voltage, comprising at least one bias switch, coupled to the bias capacitor and the current source circuit, wherein the bias voltage charges the bias capacitor when the bias switch circuit is conducted. The present invention further discloses a DAC applying the output stage circuit and a TOF system applying the DAC. The conventional kick back issue can be improved by the mechanism provided by the present invention.

公开(公告)号：US20240005944A1

公开(公告)日：2024-01-04

申请号：US17810172

申请日：2022-06-30

Applicant: David R. Baraff

Inventor： David R. Baraff ,  Gene Kang

IPC: G10L21/057 ,  G06N3/04 ,  H03M1/82

CPC classification number: G10L21/057 ,  G06N3/0454 ,  H03M1/82

Abstract: Real-time speech output with improved intelligibility are described. One example embodiment includes a device. The device includes a microphone configured to capture one or more frames of unintelligible speech from a user. The device also includes an analog-to-digital converter (ADC) configured to convert the one or more captured frames of unintelligible speech into a digital representation. Additionally, the device includes a computing device. The computing device is configured to receive the digital representation from the ADC. The computing device is also configured to apply a machine-learned model to the digital representation to generate one or more frames with improved intelligibility. Further, the computing device is configured to output the one or more frames with improved intelligibility. In addition, the device includes a digital-to-analog converter (DAC) configured to convert the one or more frames with improved intelligibility into an analog form. Yet further, the device includes a speaker.

公开(公告)号：US11243078B2

公开(公告)日：2022-02-08

申请号：US16361680

申请日：2019-03-22

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Chihchuan Che ,  Yaesuk Jeong

IPC: G01C19/5776 ,  H03M1/06 ,  H03M1/08 ,  H03M1/18 ,  H03M1/50 ,  H03M1/82

Abstract: A signal processing circuit for a gyroscope apparatus is disclosed. The signal processing circuit includes a first electrode and a second electrode pairing with the first electrode. The signal processing circuit, being a negative feedback loop circuit, is configured to be connected with the first electrode and the second electrode and comprises a demodulator configured to convert a current from the first electrode into a voltage and demodulate the converted voltage to output a demodulated signal, an analog-to-digital converter configured to convert the demodulated signal from the demodulator into a digital signal, a proportional-integral-derivative controller that is connected to the analog-to-digital converter, a digital-to-analog converter configured to convert an output signal from the proportional-integral-derivative controller to an analog signal, and a modulator configured to be electrically connected with the second electrode and to be electrically connected with the digital-to-analog converter.

公开(公告)号：US11184018B1

公开(公告)日：2021-11-23

申请号：US17087234

申请日：2020-11-02

Applicant: QUALCOMM Incorporated

Inventor： Xilin Liu ,  Parisa Mahmoudidaryan ,  Shahin Mehdizad Taleie ,  Negar Rashidi ,  Dongwon Seo

IPC: H03M1/18 ,  H03M1/82 ,  H03M1/06 ,  H03M1/10 ,  H03K5/156 ,  H03K5/05 ,  H03M1/80 ,  H03K5/00

Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. For example, certain aspects provide an apparatus for digital-to-analog conversion. The apparatus generally includes a mixing-mode digital-to-analog converter (DAC), a duty cycle adjustment circuit having an input coupled to an input clock node and having an output coupled to a clock input of the mixing-mode DAC, and a current comparison circuit having inputs coupled to outputs of the mixing-mode DAC and having an output coupled to a control input of the duty cycle adjustment circuit.