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公开(公告)号：WO2019133172A1
公开(公告)日：2019-07-04
申请号：PCT/US2018/063054
申请日：2018-11-29
Applicant: INTEL CORPORATION
Inventor： WEISSMANN, Eliezer , GENDLER, Alexander , ROTEM, Efraim , COHEN, Moshe , MALLICK, Asit K. , BRANDT, Jason, W. , SUBRAMANIAM, Kameswar , FELLMAN, Nathan , SHAFI, Hisham
IPC: G06F13/36
Abstract: Processor, method, and system for reducing latency in accessing remote registers is described herein. One embodiment of a processor includes one or more remote registers and remote register access circuitry. The remote register access circuitry is to detect a request from the requestor to access a first register of the one or more remote registers, access to the first register in accordance to the request without the requestor having to wait for completion of the access, and provide a notification accessible to the requestor upon completion of the access to the first register of the one or more remote registers.
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公开(公告)号：WO2019040050A1
公开(公告)日：2019-02-28
申请号：PCT/US2017/048059
申请日：2017-08-22
Applicant: INTEL CORPORATION
Inventor： ROTEM, Efraim , WEISSMANN, Eliezer , RAJWAN, Doron , AIZIK, Yoni , NATANZON, Esfir , ROSENZWEIG, Nir , SHULMAN, Nadav , PLACKLE, Bart
Abstract: Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.
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公开(公告)号：WO2014105148A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/046863
申请日：2013-06-20
Applicant: INTEL CORPORATION
Inventor： BEN-KIKI, Oren , PARDO, Ilan , VALENTINE, Robert , WEISSMANN, Eliezer , MARKOVICH, Dror , YOSEF, Yuval
CPC classification number: G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/384 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F9/54 , G06F11/0721 , G06F11/0724 , G06F11/0772 , G06F12/0875 , G06F2212/452
Abstract: An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the commend could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands; and one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data.
Abstract translation: 描述了一种用于提供加速器的低延迟调用的装置和方法。 例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或指示不能执行推荐的原因的数据; 执行逻辑以执行包括调用一个或多个加速器命令的加速器调用指令的多个指令; 以及一个或多个加速器，用于从命令寄存器读取命令数据，并且响应地尝试执行由命令数据识别的命令。
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4.发明申请MIGRATING TASKS BETWEEN ASYMMETRIC COMPUTING ELEMENTS OF A MULTI-CORE PROCESSOR 审中-公开多核处理器的不对称计算元素之间的迁移任务
公开(公告)号：WO2013162589A1
公开(公告)日：2013-10-31
申请号：PCT/US2012/035339
申请日：2012-04-27
Applicant: INTEL CORPORATION , NAVEH, Alon , YOSEF, Yuval , WEISSMANN, Eliezer , AGGARWAL, Anil , ROTEM, Efraim , MENDELSON, Avi , RONEN, Ronny , GINZBURG, Boris , MISHAELI, Michael , HAHN, Scott D. , KOUFATY, David A. , SRINIVASA, Ganapati , THERIEN, Guy
Inventor： NAVEH, Alon , YOSEF, Yuval , WEISSMANN, Eliezer , AGGARWAL, Anil , ROTEM, Efraim , MENDELSON, Avi , RONEN, Ronny , GINZBURG, Boris , MISHAELI, Michael , HAHN, Scott D. , KOUFATY, David A. , SRINIVASA, Ganapati , THERIEN, Guy
CPC classification number: G06F9/30145 , G06F9/4856 , G06F9/5094 , G06F2209/5018 , Y02D10/22 , Y02D10/24 , Y02D10/32
Abstract: In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有第一和第二核心以独立执行指令的多核处理器，操作系统（OS）可见的第一核心和对OS可透明的第二核心，并且与第一核心不同。 可以包括在多核处理器中或耦合到多核处理器的任务控制器可以使由OS所安排的第一进程到OS的第一核心到第二核心的动态迁移到第二核心。 描述和要求保护其他实施例。
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5.发明申请A METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING OPTIMIZING C-STATE SELECTION UNDER VARIABLE WAKEUP RATES 审中-公开包括在可变唤醒率下优化C状态选择的能量效率和节能方法，装置和系统
公开(公告)号：WO2013101906A2
公开(公告)日：2013-07-04
申请号：PCT/US2012/071776
申请日：2012-12-27
Applicant: INTEL CORPORATION
Inventor： NAVEH, Alon , WEISSMANN, Eliezer , NATHAN, Ofer , SHULMAN, Nadav
IPC: G06F1/32
CPC classification number: G06F1/3275 , G06F1/3203 , G06F1/3206 , G06F1/3243 , G06F1/3246 , G06F1/3296 , Y02D10/152 , Y02D10/172
Abstract: A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1 ) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.
Abstract translation: 处理器可以包括功率管理技术以动态地为处理核心选择最佳C-状态。 对OS上实际工作负载的测量表现出两个重要观察结果（1）高中断率突发散布在低中断率时段和长时段高活动水平之间; （2）中断率可能突然下降到当前操作系统（OS）典型值的中断率（例如1毫秒）以下。 基于存储在计数器中的陈旧数据来确定C状态，功率控制逻辑可以通过超越由OS或任何其他功率监视逻辑确定的C状态来确定最佳C状态。 功率控制逻辑可动态地基于CPU空闲驻留时间和可变速率唤醒事件来确定最佳C-状态以匹配预期唤醒事件速率。
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Patent Agency Ranking
公开(公告)号：WO2013101069A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067851
申请日：2011-12-29
Applicant: INTEL CORPORATION , YAMADA, Koichi , GINZBURG, Boris , LI, Wei , RONEN, Ronny , NATANZON, Esfir , LEVIT-GUREVICH, Konstantin , HABER, Gadi , NAVEH, Alon , WEISSMANN, Eliezer , MISHAELI, Michael
Inventor： YAMADA, Koichi , GINZBURG, Boris , LI, Wei , RONEN, Ronny , NATANZON, Esfir , LEVIT-GUREVICH, Konstantin , HABER, Gadi , NAVEH, Alon , WEISSMANN, Eliezer , MISHAELI, Michael
CPC classification number: G06F9/30181 , G06F9/5044 , G06F9/5094 , Y02D10/22
Abstract: An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on the ASMP is analyzed by a binary analysis unit to determine what functions are called by the program code and select which of the cores are to execute the program code, or a code segment thereof. Selection may be made to provide for native execution of the program code, to minimize power consumption, and so forth. Control operations based on this selection may then be inserted into the program code, forming instrumented program code. The instrumented program code is then executed by the ASMP.
Abstract translation: 非对称多处理器系统（ASMP）可以包括实现不同指令集架构并具有不同功率需求的计算核心。 在ASMP上执行的程序代码由二进制分析单元进行分析，以确定程序代码调用哪些函数，并选择哪些核执行程序代码或其代码段。 可以进行选择以提供程序代码的本地执行，以最小化功耗等等。 可以将基于该选择的控制操作插入到程序代码中，形成检测程序代码。 然后由ASMP执行检测的程序代码。
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公开(公告)号：WO2013077890A1
公开(公告)日：2013-05-30
申请号：PCT/US2011/068198
申请日：2011-12-30
Applicant: INTEL CORPORATION , THERIEN, Guy M. , DIEFENBAUGH, Paul S. , AGGARWAL, Anil , HENROID, Andrew D. , SHRALL, Jeremy J. , ROTEM, Efraim , SISTLA, Krishnakanth V. , WEISSMANN, Eliezer
Inventor： THERIEN, Guy M. , DIEFENBAUGH, Paul S. , AGGARWAL, Anil , HENROID, Andrew D. , SHRALL, Jeremy J. , ROTEM, Efraim , SISTLA, Krishnakanth V. , WEISSMANN, Eliezer
CPC classification number: G06F9/4403 , G06F1/206 , G06F1/26 , G06F1/28 , G06F1/32 , G06F1/3203 , G06F1/3234 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/22 , G06F9/30098 , G06F9/3012 , G06F9/384 , G06F9/44 , G06F9/4401 , G06F9/4418 , G06F9/445 , G06F11/3024 , G06F11/3409 , G06F11/3447 , G06F11/3466 , G06F11/3664 , G06F11/3672 , G06F11/3688 , G06F15/7871 , G06F17/30339 , G06F2209/501 , G06F2217/78 , Y02D10/126 , Y02D10/172
Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
Abstract translation: 平台电力管理方案技术领域本发明涉及一种平台电力管理方案。 在一些实施例中，平台使用要由OSPM系统请求的一个或多个参数来提供相对性能等级。
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公开(公告)号：WO2012125201A1
公开(公告)日：2012-09-20
申请号：PCT/US2011/067963
申请日：2011-12-29
Applicant: INTEL CORPORATION , GINZBURG, Boris , NATANZON, Esfirush , OSADCHIY, Ilya , RONEN, Ronny , WEISSMANN, Eliezer , ZACH, Yoav , FARRELL, Robert, L.
Inventor： GINZBURG, Boris , NATANZON, Esfirush , OSADCHIY, Ilya , RONEN, Ronny , WEISSMANN, Eliezer , ZACH, Yoav , FARRELL, Robert, L.
CPC classification number: G06F12/08 , G06F2212/302
Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.
Abstract translation: 在图形处理单元中出现的页面错误可以由在中央处理单元上运行的操作系统来处理。 在一些实施例中，这意味着未被固定的存储器可以用于图形处理单元。 在图形处理单元中使用未固定的存储器可以在某些情况下扩展图形处理单元的能力。
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公开(公告)号：WO2006028652A2
公开(公告)日：2006-03-16
申请号：PCT/US2005/028699
申请日：2005-08-12
Applicant: INTEL CORPORATION , NAVEH, Alon , MENDELSON, Avi , ANATI, Ittai , WEISSMANN, Eliezer
Inventor： NAVEH, Alon , MENDELSON, Avi , ANATI, Ittai , WEISSMANN, Eliezer
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/3203 , Y02D10/171 , Y02D50/20
Abstract: Systems and methods of managing processors provide for detecting a command at a core of a processor having a plurality of cores, where the command requests a transition of the core to an idle state. Power consumption of the core is managed based on the command and an idle state status of each of the plurality of cores.
Abstract translation: 管理处理器的系统和方法提供用于检测具有多个核的处理器的核心处的命令，其中命令请求核到空闲状态。 基于多个核心中的每一个的命令和空闲状态来管理核心的功耗。
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公开(公告)号：WO2021011577A1
公开(公告)日：2021-01-21
申请号：PCT/US2020/042014
申请日：2020-07-14
Applicant: INTEL CORPORATION
Inventor： SAKARDA, Premanand , ROTEM, Efraim , WEISSMANN, Eliezer , ABU SALAH, Hisham , BEJA, Hadas , FENGER, Russell , GANAPATHY, Deepak , HERMERDING II, James , KARAVANY, Ido , KRISHNAKUMAR, Nivedha , NAIR, Sudheer , OLSWANG, Gilad , PERI, Moran , WAGNER, Avishai , WANG, Zhongsheng , YASSIN, Noha
IPC: G06F1/324 , G06F1/3212 , G06F1/3296 , G06F1/3293 , G06N20/00
Abstract: Described are mechanisms and methods for tracking user behavior profile over large time intervals and extracting observations for a user usage profile. The mechanisms and methods use machine learning (ML) algorithms embedded into a dynamic platform and thermal framework (DPTF) (e.g., Dynamic Tuning Technology) and predict device workloads using hardware (HW) counters. These mechanisms and methods may accordingly increase performance and user responsiveness by dynamically changing an Energy Performance Preference (EPP) based on a longer time workload analysis and workload prediction.
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