公开(公告)号：WO2006052958A2

公开(公告)日：2006-05-18

申请号：PCT/US2005/040414

申请日：2005-11-08

Applicant: EPION CORPORATION ,  GEFFKEN, Robert, M. ,  HAUTALA, John, J. ,  SHERMAN, Steven, R. ,  LEARN, Arthur, J.

Inventor： GEFFKEN, Robert, M. ,  HAUTALA, John, J. ,  SHERMAN, Steven, R. ,  LEARN, Arthur, J.

IPC: H01L21/44

CPC classification number: H01L21/76867 ,  C23C14/0605 ,  C23C14/0635 ,  C23C14/0652 ,  C23C14/221 ,  C23C16/26 ,  C23C16/325 ,  C23C16/345 ,  C23C16/513 ,  H01J2237/0812 ,  H01L21/02074 ,  H01L21/02301 ,  H01L21/02304 ,  H01L21/321 ,  H01L21/32136 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76883 ,  H01L21/76886 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Capping layer or layers on a surface of a copper interconnect wiring layer for use in interconnect structures for integrated circuits and methods of forming improved integration interconnection structures for integrated circuits by the application of gas-cluster ion-beam processing. Reduced copper diffusion and improved electromigration lifetime result and the use of selective metal capping techniques and their attendant yield problems are avoided.

Abstract translation: 在用于集成电路的互连结构中的铜互连布线层的表面上的覆盖层或层，以及通过应用气体簇离子束处理形成用于集成电路的改进的集成互连结构的方法。 减少铜扩散和改善电迁移寿命，避免使用选择性金属封盖技术及其伴随的产量问题。

公开(公告)号：WO2005103321A3

公开(公告)日：2006-01-19

申请号：PCT/US2005005869

申请日：2005-02-23

Applicant: TOKYO ELECTRON LTD ,  TOKYO ELECTRON AMERICA INC ,  CERIO FRANK M JR ,  FAGUET JACQUES ,  GITTLEMAN BRUCE D ,  ROBINSON RODNEY L

Inventor： CERIO FRANK M JR ,  FAGUET JACQUES ,  GITTLEMAN BRUCE D ,  ROBINSON RODNEY L

IPC: C23C14/02 ,  C23C14/04 ,  C23C14/34 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L21/2855 ,  C23C14/025 ,  C23C14/046 ,  C23C14/345 ,  C23C14/3492 ,  H01J37/32706 ,  H01J2237/3327 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L2221/1078 ,  H01L2221/1089

Abstract: An iPVD System (200) is programmed to deposit uniform material, such as barrier material (912), into high aspect ratio nano-size features (11) on semiconductor substrates (21) using a process which enhances the sidewall (16) coverage compared to the field (10) and bottom (15) coverage(s) while minimizing or eliminating overhang (14) within a vacuum chamber (30). The iPVD system (200) is operated at low target power and high pressure >50mT to sputter material from the target. RF energy is coupled into the chamber to form a high density plasma. A small RF bias (less than a few volts) can be applied to aid in enhancing the coverage, especially at the bottom.

Abstract translation: iPVD系统（200）被编程为使用增强侧壁（16）覆盖的过程将诸如阻挡材料（912）的均匀材料沉积到半导体衬底（21）上的高纵横比纳米尺寸特征（11）中 （10）和底部（15）覆盖，同时最小化或消除真空室（30）内的悬垂（14）。 iPVD系统（200）以低目标功率和高压> 50mT运行，以从目标溅射材料。 RF能量耦合到腔室中以形成高密度等离子体。 可以应用小的RF偏压（小于几伏）来帮助增强覆盖范围，特别是在底部。

公开(公告)号：WO2005106946A1

公开(公告)日：2005-11-10

申请号：PCT/EP2005/051808

申请日：2005-04-22

Applicant: INFINEON TECHNOLOGIES AG ,  AUBEL, Oliver ,  HASSE, Wolfgang ,  HOMMEL, Martina ,  KÖRNER, Heinrich

Inventor： AUBEL, Oliver ,  HASSE, Wolfgang ,  HOMMEL, Martina ,  KÖRNER, Heinrich

IPC: H01L21/768

CPC classification number: H01L21/76864 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Erläutert werden unter anderem Verfahren, bei denen durch langes Tempern Barrierematerial an einem Viaboden oder an einer Viadeckfläche entfernt werden. Gleichzeitig oder alternativ werden durch das lange Tempern Leitbahnen (106) mit Barrierematerial (110) auf einfache und unkomplizierte Weise beschichtet.

Abstract translation: 被描述，特别是方法，其中，由长退火的阻挡材料或ViabodenViadeckfläche除去。 同时或交替地（106）通过所述长退火互连涂覆以简单和直接的方式的阻隔材料（110）。

公开(公告)号：WO2005048342A1

公开(公告)日：2005-05-26

申请号：PCT/US2004/033417

申请日：2004-10-08

Applicant: ADVANCED MICRO DEVICES, INC. ,  HOPPER, Dawn, M. ,  KINOSHITA, Hiroyuki ,  WOO, Christy

Inventor： HOPPER, Dawn, M. ,  KINOSHITA, Hiroyuki ,  WOO, Christy

IPC: H01L21/768

CPC classification number: H01L21/76844 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76865

Abstract: According to one exemplary embodiment, a method for forming a contact over a silicide layer (214) situated in a semiconductor die comprises a step of depositing a barrier layer (202) on sidewalls (206,207) of a contact hole (208) and on a native oxide layer (210) situated at a bottom of the contact hole (208), where the sidewalls (206,207) are defined by the contact hole (208) in a dielectric layer (204). The step of depositing (150) the barrier layer (202) on the sidewalls (206,207) of the contact hole (208) and on the native oxide layer (210) can be optimized such that the barrier layer (202) has a greater thickness at a top of the contact hole (208) than a thickness at the bottom of the contact hole (208). According to this exemplary embodiment, the method further comprises a step of removing (152) a portion (219) of the barrier layer (202) and the native oxide layer (210) situated at the bottom of the contact hole (208) to expose the silicide layer (214).

Abstract translation: 根据一个示例性实施例，用于在位于半导体管芯中的硅化物层（214）上形成接触的方法包括在接触孔（208）的侧壁（206,207）上沉积阻挡层（202）的步骤， 位于接触孔（208）的底部的天然氧化物层（210），其中侧壁（206,207）由电介质层（204）中的接触孔（208）限定。 可以优化将阻挡层（202）沉积在接触孔（208）的侧壁（206,207）上和在自然氧化物层（210）上的步骤，使得阻挡层（202）具有更大的厚度 在接触孔（208）的顶部处比接触孔（208）底部的厚度高。 根据该示例性实施例，该方法还包括去除（152）阻挡层（202）的部分（219）和位于接触孔（208）底部的自然氧化物层（210）暴露的步骤 硅化物层（214）。

公开(公告)号：WO2004095513A3

公开(公告)日：2005-01-20

申请号：PCT/US2004011865

申请日：2004-04-16

Applicant: FREESCALE SEMICONDUCTOR INC ,  ZHENG DA ,  DENNING DEAN J ,  VENTZEK PETER L G

Inventor： ZHENG DA ,  DENNING DEAN J ,  VENTZEK PETER L G

IPC: C23C14/04 ,  C23C14/34 ,  H01L21/285 ,  H01L21/768 ,  C23C14/32

CPC classification number: H01L21/76843 ,  C23C14/046 ,  C23C14/345 ,  C23C14/3492 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/76862 ,  H01L21/76865

Abstract: A method for depositing a barrier or coating layer (34) in a semiconductor recessed structure (28) within a substrate (20) using a plasma process (62) that includes alternating depositing steps (64) and resputtering steps (66). The depositing step (64) deposits a barrier layer (34), including a thick bottom region (38) and a sidewall region (40) along the recessed structure (28) surface. The resputtering step (66) reduces the barrier layer (34) thickness in the bottom region (38) and increases the barrier layer (34) thickness in the otherwise thinly covered portions of the substrate sidewall region (40). Control of powers ranges supplied to the sputtering target (14) and the substrate (20) achieve the depositing and resputtering steps. The process applies also to other coating layers than barrier layers (34), providing a uniform sidewall coverage and thin bottom coverage, e.g., for permalloy deposition in MRAM devices and dual gate electrode formation in CMOS devices.

Abstract translation: 一种使用包括交替沉积步骤（64）和再溅射步骤（66）的等离子体处理（62）在衬底（20）内的半导体凹陷结构（28）中沉积阻挡层或涂层（34）的方法。 沉积步骤（64）沿着凹陷结构（28）表面沉积包括厚底部区域（38）和侧壁区域（40）的阻挡层（34）。 重新溅射步骤（66）减小了底部区域（38）中的阻挡层（34）的厚度，并增加了衬底侧壁区域（40）的其它薄的覆盖部分中的阻挡层（34）的厚度。 控制提供给溅射靶（14）和基板（20）的功率范围实现沉积和再溅射步骤。 该方法也适用于除阻挡层（34）以外的其它涂层，提供均匀的侧壁覆盖和薄的底部覆盖，例如用于MRAM器件中的坡莫合金沉积和CMOS器件中的双栅电极形成。

公开(公告)号：WO2004061933B1

公开(公告)日：2004-11-25

申请号：PCT/US0341263

申请日：2003-12-24

Applicant: LEXMARK INT INC

Inventor： BELL BYRON VENCENT ,  GUAN YIMIN

IPC: B41J2/14 ,  B41J2/16 ,  H01L21/768 ,  H01L21/4763 ,  H01L23/48

CPC classification number: H01L21/76843 ,  B41J2/14129 ,  B41J2/1601 ,  B41J2/1626 ,  B41J2/1631 ,  B41J2/1646 ,  B41J2202/03 ,  B41J2202/13 ,  H01L21/76865

Abstract: A semiconductor device containing at least one transistor (14) and at least one heater resistor (18) in a heater resistor area adjacent the at least one transistor on a semiconductor substrate (22). The device includes a silicon substrate (22) containing contact openings for metal contacts (34) to the at least one transistor. A barrier layer (42) is in the contact openings and in the heater resistor area and provides a diffusion barrier/heater resistor layer. The barrier layer is selected from a group consisting of TaN, Ta/TaAl, TaN/TaAl, TiWN, TaAlN, TiN, Ta(Nx, Oy), WSi(Nx, Oy), TaSi, TaSiN, WSiN, and TaSi(Nx, Oy). A conductive layer (44) is adjacent at least a portion of the barrier layer for providing connection between a power source and the at least one heater resistor and at least one transistor. The semiconductor device is devoid of a patterned and etched barrier layer in the heater resistor area.

Abstract translation: 一种半导体器件，在半导体衬底（22）上的与至少一个晶体管相邻的加热器电阻器区域中包含至少一个晶体管（14）和至少一个加热电阻器（18）。 该器件包括硅衬底（22），该硅衬底包含用于与至少一个晶体管的金属触点（34）的接触开口。 阻挡层（42）位于接触开口中和加热电阻器区域中，并提供扩散阻挡层/加热器电阻层。 阻挡层选自由TaN，Ta / TaAl，TaN / TaAl，TiWN，TaAlN，TiN，Ta（Nx，Oy），WSi（Nx，Oy），TaSi，TaSiN，WSiN和TaSi（Nx ，Oy）。 导电层（44）与阻挡层的至少一部分相邻，用于提供电源与至少一个加热器电阻器和至少一个晶体管之间的连接。 半导体器件在加热器电阻器区域中没有图案化和蚀刻的阻挡层。

公开(公告)号：WO2004095513A2

公开(公告)日：2004-11-04

申请号：PCT/US2004/011865

申请日：2004-04-16

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ZHANG, Du ,  DENNING, Dean, J. ,  VENTZEK, Peter, L. G.

Inventor： ZHANG, Du ,  DENNING, Dean, J. ,  VENTZEK, Peter, L. G.

IPC: H01L

CPC classification number: H01L21/76843 ,  C23C14/046 ,  C23C14/345 ,  C23C14/3492 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/76862 ,  H01L21/76865

Abstract: A method for depositing a barrier or coating layer (34) in a semiconductor recessed structure (28) within a substrate (20) using a plasma process (62) that includes alternating depositing steps (64) and resputtering steps (66). The depositing step (64) deposits a barrier layer (34), including a thick bottom region (38) and a sidewall region (40) along the recessed structure (28) surface. The resputtering step (66) reduces the barrier layer (34) thickness in the bottom region (38) and increases the barrier layer (34) thickness in the otherwise thinly covered portions of the substrate sidewall region (40). Control of powers ranges supplied to the sputtering target (14) and the substrate (20) achieve the depositing and resputtering steps. The process applies also to other coating layers than barrier layers (34), providing a uniform sidewall coverage and thin bottom coverage, e.g., for permalloy deposition in MRAM devices and dual gate electrode formation in CMOS devices.

Abstract translation: 一种使用包括交替沉积步骤（64）和再溅射步骤（66）的等离子体处理（62）在衬底（20）内的半导体凹陷结构（28）中沉积阻挡层或涂层（34）的方法。 沉积步骤（64）沿凹陷结构（28）表面沉积包括厚底部区域（38）和侧壁区域（40）的阻挡层（34）。 重新溅射步骤（66）减小了底部区域（38）中的阻挡层（34）厚度，并增加了衬底侧壁区域（40）的其它薄的覆盖部分中的阻挡层（34）的厚度。 控制提供给溅射靶（14）和基板（20）的功率范围实现沉积和再溅射步骤。 该方法也适用于除阻挡层（34）以外的其它涂层，提供均匀的侧壁覆盖和薄的底部覆盖，例如用于MRAM器件中的坡莫合金沉积和CMOS器件中的双栅电极形成。

公开(公告)号：WO2004061933A1

公开(公告)日：2004-07-22

申请号：PCT/US2003/041263

申请日：2003-12-24

Applicant: LEXMARK INTERNATIONAL, INC.

Inventor： BELL, Byron, Vencent ,  GUAN, Yimin

IPC: H01L21/4763

CPC classification number: H01L21/76843 ,  B41J2/14129 ,  B41J2/1601 ,  B41J2/1626 ,  B41J2/1631 ,  B41J2/1646 ,  B41J2202/03 ,  B41J2202/13 ,  H01L21/76865

Abstract: A semiconductor device containing at least one transistor (14) and at least one heater resistor (18) in a heater resistor area adjacent the at least one transistor on a semiconductor substrate (22). The device includes a silicon substrate (22) containing contact openings for metal contacts (34) to the at least one transistor. A barrier layer (42) is in the contact openings and in the heater resistor area and provides a diffusion barrier/heater resistor layer. The barrier layer is selected from a group consisting of TaN, Ta/TaAl, TaN/TaAl, TiWN, TaAlN, TiN, Ta(N x , O y ), WSi(N x , O y ), TaSi, TaSiN, WSiN, and TaSi(N x , O y ). A conductive layer (44) is adjacent at least a portion of the barrier layer for providing connection between a power source and the at least one heater resistor and at least one transistor. The semiconductor device is devoid of a patterned and etched barrier layer in the heater resistor area.

Abstract translation: 一种在与半导体衬底（22）上的所述至少一个晶体管相邻的加热电阻器区域中包含至少一个晶体管（14）和至少一个加热电阻器（18）的半导体器件。 该器件包括硅衬底（22），其包含用于至少一个晶体管的金属触点（34）的接触开口。 阻挡层（42）位于接触开口和加热电阻区域中，并提供扩散阻挡层/加热电阻层。 阻挡层选自TaN，Ta / TaAl，TaN / TaAl，TiWN，TaAlN，TiN，Ta（Nx，Oy），WSi（Nx，Oy），TaSi，TaSiN，WSiN和TaSi（Nx ，Oy）。 导电层（44）与阻挡层的至少一部分相邻，用于提供电源与至少一个加热电阻器和至少一个晶体管之间的连接。 半导体器件在加热电阻器区域中没有图案化和蚀刻的阻挡层。

公开(公告)号：WO2004053926A2

公开(公告)日：2004-06-24

申请号：PCT/EP2003/050958

申请日：2003-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM DEUTSCHLAND GMBH

Inventor： MALHOTRA, Sandra ,  SIMON, Andrew

IPC: H01L

CPC classification number: H01L21/76844 ,  H01L21/76805 ,  H01L21/76865

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.

Abstract translation: 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体被介电层覆盖。 图案化电介质层以暴露金属导体。 然后将衬垫层沉积到图案中。 然后对衬垫层进行氩溅射蚀刻以去除衬里层并暴露金属导体。 在氩溅射蚀刻的过程中，衬里层被再沉积到图案的侧壁上。 最后，附加层沉积到图案中并覆盖再沉积的衬里层。

公开(公告)号：WO2003072846A1

公开(公告)日：2003-09-04

申请号：PCT/GB2003/000696

申请日：2003-02-14

Applicant: TRIKON TECHNOLOGIES LIMITED ,  BURGESS, Stephen, Robert ,  DONOHUE, Hilke

Inventor： BURGESS, Stephen, Robert ,  DONOHUE, Hilke

IPC: C23C14/06

CPC classification number: H01L21/76843 ,  C23C14/046 ,  C23C14/0641 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76865 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of depositing a barrier layer on a substrate having a recess, including sputtering Tantalum in a nitrogen atmosphere wherein the flow of nitrogen is selected to deposit mixed phase bcc/βTa and wherein the sputtered ions are sufficiently energetic to cause re-sputtering of deposited material from the base of the recess to its sidewall or sidewalls.

Abstract translation: 一种在具有凹陷的衬底上沉积阻挡层的方法，包括在氮气气氛中溅射钽，其中选择氮气流以沉积混合相bcc /βTa，并且其中溅射离子具有足够的能量以引起沉积的重新溅射 材料从凹槽的底部到其侧壁或侧壁。