公开(公告)号：WO1988007290A1

公开(公告)日：1988-09-22

申请号：PCT/US1988000735

申请日：1988-03-08

Applicant: INMOS CORPORATION

Inventor： INMOS CORPORATION ,  MOBLEY, Kenneth, J.

IPC: H03K05/24

CPC classification number: H03K5/2481 ,  G11C7/062 ,  G11C2207/063 ,  H03K5/249

Abstract: An amplifier (10) for a semiconductor circuit provides two circuit paths between VCC and ground, each including the source-drain path of a corresponding primary transistor (23, 28). Two impedances (16, 18) are coupled to respective inputs (12, 14). The primary transistors are kept in saturation so that the voltage differential is developed at outputs (38, 40) located along the two circuit paths. Also, a clamp circuit has a common node (30) coupling the gate electrodes of the primary transistors together. Secondary transistors (24, 26) are included to mimic voltage changes on either input.

公开(公告)号：WO2016018247A1

公开(公告)日：2016-02-04

申请号：PCT/US2014/048580

申请日：2014-07-29

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： BUCHANAN, Brent

IPC: G11C7/06 ,  G11C5/14

CPC classification number: G11C13/004 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2207/063

Abstract: An example device in accordance with an aspect of the present disclosure includes a first module, a second module, and a third module. The first module is to compare an input current to a first reference current, and provide a first output. The second module is to compare the input current to a second reference current, and provide a second output. The third module is to compare the first output to the second output, and provide a third output indicative of a state associated with the input current.

Abstract translation: 根据本公开的一个方面的示例性设备包括第一模块，第二模块和第三模块。 第一模块是将输入电流与第一参考电流进行比较，并提供第一输出。 第二模块是将输入电流与第二参考电流进行比较，并提供第二输出。 第三模块是将第一输出与第二输出进行比较，并提供指示与输入电流相关联的状态的第三输出。

公开(公告)号：WO2014190046A1

公开(公告)日：2014-11-27

申请号：PCT/US2014/038954

申请日：2014-05-21

Applicant: SANDISK 3D LLC

Inventor： SIAU, Chang ,  JIANG, Xiaowei ,  CHEN, Yingchang

IPC: G11C16/24 ,  G11C16/26 ,  G11C11/56 ,  G11C13/00 ,  G11C7/06 ,  G11C7/14 ,  G11C7/04 ,  G11C7/12

CPC classification number: G11C13/004 ,  G11C7/04 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C11/5642 ,  G11C13/0069 ,  G11C16/24 ,  G11C16/26 ,  G11C2013/0042 ,  G11C2013/0045 ,  G11C2207/063

Abstract: Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for setting a bit line to a read voltage prior to sensing a memory cell connected to the bit line. The bit line precharge circuit may include a first transistor in a source-follower configuration with a first gate and a first source node electrically coupled to the bit line. By applying local feedback from the first source node to the first gate, the bit line settling time may be reduced. In some cases, a first voltage applied to the first gate may be determined based on a first current drawn from the first bit line. Thus, the first voltage applied to the first gate may vary over time depending on the conductivity of a selected memory cell connected to the bit line.

Abstract translation: 描述了使用闭环反馈对位线进行预充电的方法。 在一个实施例中，读出放大器可以包括位线预充电电路，用于在感测连接到位线的存储器单元之前将位线设置为读取电压。 位线预充电电路可以包括具有第一栅极的源极跟随器配置的第一晶体管和电耦合到位线的第一源节点。 通过将来自第一源节点的局部反馈应用于第一栅极，可以减少位线建立时间。 在一些情况下，施加到第一栅极的第一电压可以基于从第一位线汲取的第一电流来确定。 因此，施加到第一栅极的第一电压可以随时间而变化，这取决于连接到位线的所选存储器单元的电导率。

公开(公告)号：WO2014070366A1

公开(公告)日：2014-05-08

申请号：PCT/US2013/063272

申请日：2013-10-03

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： ZHOU, Yao ,  QIAN, Xiaozhou ,  LIN, Guangming

IPC: G11C7/06 ,  G11C16/28

CPC classification number: G11C11/5642 ,  G05F3/262 ,  G11C5/147 ,  G11C7/062 ,  G11C7/12 ,  G11C16/28 ,  G11C2207/063

Abstract: A non-volatile memory device with a sensing amplifier (10) that includes a current mirror comprising a pair of resistors (20,30) and an operational amplifier (40) is disclosed.

Abstract translation: 公开了一种具有感测放大器（10）的非易失性存储器件，该感测放大器（10）包括包括一对电阻器（20,30）和运算放大器（40）的电流镜。

公开(公告)号：WO2013082618A2

公开(公告)日：2013-06-06

申请号：PCT/US2012/067640

申请日：2012-12-03

Applicant: CYPRESS SEMICONDUCTOR CORPORATION ,  ZONTE, Cristinel ,  RAGHAVAN, Vijay

Inventor： ZONTE, Cristinel ,  RAGHAVAN, Vijay

IPC: G11C7/10 ,  G11C7/06

CPC classification number: G11C7/062 ,  G11C11/4091 ,  G11C2207/063

Abstract: Memory circuits and systems are provided. One memory circuit includes an active memory device, an inactive memory device, and a sense amplifier coupled between the active memory device and the inactive memory device. A reference current is coupled between the inactive memory device and the sense amplifier. The active memory device and the inactive memory device are the same type of memory device and the inactive memory device is a reference device with respect to the active memory device's current. A memory system includes a plurality of the above memory circuit coupled to one another. Methods for sensing current in a memory circuit are also provided. One method includes supplying power to a first memory device and comparing the amount of current in the first memory device and a reference current coupled to a second memory device that is the same type of memory device as the first memory device.

Abstract translation: 提供存储器电路和系统。 一个存储器电路包括有源存储器件，非活动存储器件和耦合在有源存储器件与非活性存储器件之间的读出放大器。 参考电流耦合在非活动存储器件和读出放大器之间。 有源存储器件和非活动存储器件是相同类型的存储器件，而非活动存储器件是相对于有效存储器件电流的参考器件。 存储器系统包括彼此耦合的多个上述存储器电路。 还提供了用于感测存储器电路中的电流的方法。 一种方法包括向第一存储设备供电并比较第一存储设备中的电流量和耦合到作为与第一存储器设备相同类型的存储设备的第二存储设备的参考电流。

公开(公告)号：WO2013026044A1

公开(公告)日：2013-02-21

申请号：PCT/US2012/051489

申请日：2012-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HIRST, Jeremy ,  CASTRO, Hernan ,  TANG, Stephan

IPC: G11C7/10 ,  G11C5/14

CPC classification number: G11C13/004 ,  G11C7/06 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0059 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2207/063

Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.

Abstract translation: 本文公开的示例主题涉及用于其中的装置和/或装置和/或其中使用的各种方法，其中响应于已经发生快速恢复事件的确定，电路的电位的施加可以被启动并随后改变 在电路中。 例如，电路可以包括作为所施加的电势的结果可能经历回跳事件的存储器单元。 在某些示例实现中，可以提供感测电路，其响应于在存储器单元中发生的快速恢复事件以产生反馈信号，以启动施加到存储器单元的电位的变化。

公开(公告)号：WO2012009266A1

公开(公告)日：2012-01-19

申请号：PCT/US2011/043540

申请日：2011-07-11

Applicant: SANDISK TECHNOLOGIES, INC. ,  YI, Yan

Inventor： YI, Yan

IPC: G11C11/56 ,  G11C16/24

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/063 ,  G11C2211/5641

Abstract: Techniques are disclosed herein for efficiently operating memory arrays of non-volatile storage devices. In one embodiment, when reading data from an MLC block, reading is sped up by not discharging bit lines between successive sensing operations. For example, all even bit lines are charged up and odd bit lines are grounded to set up sensing of memory cells that are associated with a first word line and the even bit lines. Then, memory cells associated with the first word line and the even bit lines are read by, for example, sensing the even bit lines. Then, while the even bit lines are still charged, memory cells associated with another word line and the even bit lines are read. Because the even bit lines remain charged between the two sensing operations, time is saved in not having to re-charge the bit lines to an appropriate level for sensing.

Abstract translation: 本文公开了用于有效地操作非易失性存储设备的存储器阵列的技术。 在一个实施例中，当从MLC块读取数据时，通过在相继的感测操作之间不排放位线来加速读取。 例如，所有偶数位线都被充电，并且奇数位线接地以设置与第一字线和偶数位线相关联的存储器单元的感测。 然后，通过例如感测偶数位线读取与第一字线和偶数位线相关联的存储单元。 然后，当偶数位线仍然被充电时，读取与另一个字线和偶数位线相关联的存储器单元。 由于偶数位线在两个感测操作之间保持充电，所以节省时间不必将位线重新充电到用于感测的适当电平。

公开(公告)号：WO2008021655A3

公开(公告)日：2008-12-04

申请号：PCT/US2007074009

申请日：2007-07-20

Applicant: ATMEL CORP ,  FORT JIMMY ,  DAGA JEAN-MICHEL

Inventor： FORT JIMMY ,  DAGA JEAN-MICHEL

IPC: G11C7/00

CPC classification number: G11C7/067 ,  G11C7/14 ,  G11C16/26 ,  G11C16/28 ,  G11C2207/063

Abstract: A sense amplifier circuit (10) and a method for reading a memory cell. A circuit comprises a bit line (46) associated with a memory cell. A first input of a latch (12) is coupled to the bit line and a second input of the latch is coupled to a second node (32) of a dummy bit line (48). There is a means for biasing (24, 26, 38, 40) the first input and the second input of the latch to a differential voltage between the first node (30) coupled to the bit line and the second node. There is also a means for switching (52, 54, 56, 78) the latch according to memory cell current. There is also a means (74, 66, 68) for producing an output signal (dout) indicating the direction of switch. A method of reading a memory cell comprises precharging a bit line which is associated with a memory cell. The memory cell current is driven according to the programmed state of the memory cell. Latch circuitry is biased based on a differential voltage between a first node coupled to the bit line and a second node. The latch circuitry is then activated and the latch circuitry switches according to the memory cell current. An output signal indicating the direction of the latch circuitry's switch is then produced.

Abstract translation: 读出放大器电路（10）和读取存储单元的方法。 电路包括与存储单元相关的位线（46）。 锁存器（12）的第一输入端耦合到位线并且锁存器的第二输入端耦合到虚拟位线（48）的第二节点（32）。 存在用于将锁存器的第一输入端和第二输入端偏置（24,26,38,40）到耦合到位线的第一节点（30）和第二节点之间的差分电压的装置。 还有根据存储单元电流切换锁存器（52,54,56,78）的装置。 还有用于产生指示开关方向的输出信号（dout）的装置（74,66,68）。 读取存储器单元的方法包括预充电与存储器单元相关联的位线。 存储器单元电流根据存储器单元的编程状态而被驱动。 锁存电路基于耦合到位线的第一节点与第二节点之间的差分电压而偏置。 然后锁存电路被激活并且锁存电路根据存储单元电流进行切换。 然后产生表示锁存电路开关方向的输出信号。

公开(公告)号：WO2008014033A3

公开(公告)日：2008-11-06

申请号：PCT/US2007068100

申请日：2007-05-03

Applicant: FREESCALE SEMICONDUCTOR INC ,  CHOY JON S ,  AKHTER TAHMINA

Inventor： CHOY JON S ,  AKHTER TAHMINA

IPC: G11C7/04

CPC classification number: G11C29/02 ,  G11C7/04 ,  G11C7/062 ,  G11C7/14 ,  G11C16/28 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/063

Abstract: A memory (12) includes a plurality of memory cells (12), a sense amplifier (18) coupled to at least one of the plurality of memory cells, a temperature dependent current generator (26) comprising a plurality of selectable temperature dependent current sources (52-62) for generating a temperature dependent current, a temperature independent current generator (28) comprising a plurality of selectable temperature independent current sources (70, 72, 74) for generating a temperature independent current, and a summer (30) coupled to the temperature dependent current generator (26) and the temperature independent current generator (28) for combining the temperature dependent current and the temperature independent current to generate a reference current for use by the sense amplifier (18). A temperature coefficient of the reference current is approximately a same as a temperature coefficient of a memory cell current of at least one of the plurality of memory cells.

Abstract translation: 存储器（12）包括多个存储器单元（12），耦合到所述多个存储器单元中的至少一个的读出放大器（18），温度相关电流发生器（26），其包括多个可选择的温度相关电流源 （52-62），用于产生与温度相关的电流;温度独立电流发生器（28），包括用于产生与温度无关的电流的多个可选择的不依赖于温度的电流源（70,72,74），以及耦合 到与温度相关的电流发生器（26）和与温度无关的电流发生器（28），用于组合温度依赖电流和独立于温度的电流，以产生由读出放大器（18）使用的参考电流。 基准电流的温度系数与多个存储单元中的至少一个的存储单元电流的温度系数大致相同。

公开(公告)号：WO2008089159A2

公开(公告)日：2008-07-24

申请号：PCT/US2008/051025

申请日：2008-01-15

Applicant: ATMEL CORPORATION ,  PELLI, Gabriele ,  BEDARIDA, Lorenzo ,  FRULIO, Massimiliano ,  MANFRE', Davide

Inventor： PELLI, Gabriele ,  BEDARIDA, Lorenzo ,  FRULIO, Massimiliano ,  MANFRE', Davide

IPC: G11C7/06

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C16/28 ,  G11C2207/063

Abstract: A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.

Abstract translation: 一种用于读取存储器单元状态的读出放大器电路。 在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。 耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上 不受由第一和第二级的瞬态特性提供的电容电流分量的影响。