公开(公告)号：WO2014072769A1

公开(公告)日：2014-05-15

申请号：PCT/IB2012/056212

申请日：2012-11-07

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  PRIEL, Michael ,  KUZMIN, Dan ,  SOFER, Sergey

Inventor： PRIEL, Michael ,  KUZMIN, Dan ,  SOFER, Sergey

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/10 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C16/349 ,  G11C29/022 ,  G11C2207/2254

Abstract: An integrated circuit comprising an input/output "I/O" cell (34; 36; 38; 40) arranged to drive an output signal and an activity analysis unit (24a; 24b; 24c) arranged to generate an activity factor based on the output signal. The activity factor represents a switching activity intensity of the I/O cell, the switching activity intensity is associated with an ageing effect of the I/O cell. The circuit further comprises a calibration unit (22) arranged to generate a switching pattern signal based on the generated activity factor and an I/O calibration cell (28; 30) arranged to be driven by the switching pattern signal, wherein the switching pattern signal emulates the ageing effect of the I/O cell.

Abstract translation: 一种集成电路，包括布置成驱动输出信号的输入/输出“I / O”单元（34; 36; 38; 40）和布置成基于所述输入信号产生活动因子的活动分析单元（24a; 24b; 24c） 输出信号。 活动因子表示I / O单元的切换活动强度，开关活动强度与I / O单元的老化效应相关。 电路还包括校准单元（22），其被配置为基于所生成的活动因子产生开关模式信号，以及I / O校准单元（28; 30），被布置为由开关模式信号驱动，其中开关模式信号 模拟I / O单元的老化效果。

公开(公告)号：WO2014034084A1

公开(公告)日：2014-03-06

申请号：PCT/JP2013/005030

申请日：2013-08-26

Applicant: PS4 LUXCO S.A.R.L. ,  KITAGAWA, Katsuhiro ,  TAKAHASHI, Hiroki ,  NAKAMURA, Kohei

Inventor： KITAGAWA, Katsuhiro ,  TAKAHASHI, Hiroki ,  NAKAMURA, Kohei

IPC: H03K5/08 ,  G11C11/4093 ,  H03F3/45 ,  H03K5/24

CPC classification number: H03F1/0205 ,  G11C7/1084 ,  G11C11/4093 ,  H03F3/45076 ,  H03F2203/45182 ,  H03K5/2481

Abstract: A semiconductor device comprises a first input terminal; a second input terminal; an inverting amplifier circuit that comprises an input node connected to a first input terminal, an inverting input node connected to a second input terminal, and an output node connected to an output terminal, amplifies a difference between a first input signal supplied to the input node and a second input signal supplied to the second input terminal, and that outputs an output signal whose polarity is inverted from that of the first input signal to the output node; and a non-inverting amplifier circuit that comprises an input node connected to a second input terminal, an inverting input node connected to a first input terminal, and an output node connected to an output terminal, amplifies a difference between the first input signal and the second input signal, and that outputs an output signal whose polarity is the same as that of the first input signal to the output node.

Abstract translation: 半导体器件包括第一输入端; 第二输入端; 反相放大器电路，包括连接到第一输入端子的输入节点，连接到第二输入端子的反相输入节点和连接到输出端子的输出节点，放大提供给输入节点的第一输入信号 以及第二输入信号，其被提供给所述第二输入端，并将其极性与所述第一输入信号的极性反相的输出信号输出到所述输出节点; 以及非反相放大器电路，其包括连接到第二输入端子的输入节点，连接到第一输入端子的反相输入节点和连接到输出端子的输出节点，放大第一输入信号和 第二输入信号，并且将与第一输入信号的极性相同的输出信号输出到输出节点。

公开(公告)号：WO2013171790A1

公开(公告)日：2013-11-21

申请号：PCT/JP2012/003188

申请日：2012-05-16

Applicant: HITACHI, LTD. ,  IKEDA, Yasuhiro ,  UEMATSU, Yutaka ,  MURAOKA, Satoshi

Inventor： IKEDA, Yasuhiro ,  UEMATSU, Yutaka ,  MURAOKA, Satoshi

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C7/1057 ,  G11C7/1084

Abstract: To suppress power consumption and enhance signal quality as compared with the case where first and second semiconductor elements are terminated only by on-chip input termination resistor circuits. A first semiconductor element with a switching function and a second semiconductor element with a switching function are connected to each other with a substrate interconnection, and a resistor element is connected in parallel with the substrate interconnection. The resistor element is placed at an arbitrary position or a branch point on the signal interconnection.

Abstract translation: 与第一和第二半导体元件仅由片上输入终端电阻电路端接的情况相比，抑制功耗和提高信号质量。 具有开关功能的第一半导体元件和具有开关功能的第二半导体元件通过衬底互连彼此连接，并且电阻元件与衬底互连并联连接。 电阻元件放置在信号互连的任意位置或分支点处。

公开(公告)号：WO2013075220A1

公开(公告)日：2013-05-30

申请号：PCT/CA2012/001073

申请日：2012-11-20

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： PYEON, Hong Beom

IPC: G11C11/4076 ,  G11C11/4074 ,  G11C11/4093

CPC classification number: G11C7/1057 ,  G11C5/04 ,  G11C5/147 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C7/225

Abstract: A semiconductor device comprising (i) internal circuitry for outputting at least one internal clock signal and at least one internal data/control signal for transmission to a next device in a chain of semiconductor devices; (ii) data/control output circuitry for outputting at least one output data/control signal from the at least one internal data/control signal and for releasing the at least one output data/control signal towards the next device via at least one output data/control signal line, the at least one output data/control signal having a first dynamic range; and (iii) clock output circuitry for generating at least one output clock signal from the at least one internal clock signal and for releasing the at least one output clock signal towards the next device via at least one output clock signal line, the at least one output clock signal having a dynamic range different than the first dynamic range.

Abstract translation: 一种半导体器件，包括（i）内部电路，用于输出至少一个内部时钟信号和至少一个内部数据/控制信号，以传输到半导体器件链中的下一个器件; （ii）数据/控制输出电路，用于从所述至少一个内部数据/控制信号输出至少一个输出数据/控制信号，并且用于经由至少一个输出数据向所述下一个设备释放所述至少一个输出数据/控制信号 /控制信号线，所述至少一个输出数据/控制信号具有第一动态范围; 以及（iii）时钟输出电路，用于从所述至少一个内部时钟信号产生至少一个输出时钟信号，并且用于经由至少一个输出时钟信号线将所述至少一个输出时钟信号释放到所述下一个器件，所述至少一个 输出时钟信号具有不同于第一动态范围的动态范围。

公开(公告)号：WO2013034650A1

公开(公告)日：2013-03-14

申请号：PCT/EP2012/067435

申请日：2012-09-06

Applicant: ST-ERICSSON SA ,  BERTHOLOM, Cedric

Inventor： BERTHOLOM, Cedric

IPC: G06F13/40 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4093 ,  G11C7/02

CPC classification number: G11C11/40615 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4023 ,  G11C11/4093

Abstract: It is proposed a DRAM memory interface (40) for transmitting signals between a memory controller device (50) and a DRAM memory device (52). The DRAM memory interface comprises: data lines (44) for transmitting data signals; one or more control line(s) for transmitting control signals; one or more address line(s) for transmitting address signals; for each line, a transmitter device (41) connected to a first end of the line and a receiver device (42) connected to a second end of the line; wherein: each line is a single ended line wherein a signal transmitted on the line is referenced to a first reference voltage line (46); and - each line has an termination (Z 1 , Z 2 ) on both the first and second ends of the line by connecting a first impedance (Z 1 ) to the first end of the line and a second impedance (Z 2 ) to the second end of the line.

Abstract translation: 提出了一种用于在存储器控制器设备（50）和DRAM存储器件（52）之间传输信号的DRAM存储器接口（40）。 DRAM存储器接口包括：用于发送数据信号的数据线（44） 用于发送控制信号的一个或多个控制线; 用于发送地址信号的一个或多个地址线; 对于每条线路，连接到线路的第一端的发射机设备（41）和连接到线路的第二端的接收机设备（42） 其中：每条线是单端线，其中在该线上发送的信号参考第一参考电压线（46）; 并且 - 每条线路通过将第一阻抗（Z1）连接到线路的第一端并且将第二阻抗（Z2）连接到线路的第二端，具有在线路的第一和第二端上的终端（Z1，Z2） 线。

公开(公告)号：WO2008097997A1

公开(公告)日：2008-08-14

申请号：PCT/US2008/053082

申请日：2008-02-05

Applicant: RAMBUS INC. ,  LAMBRECHT, Frank

Inventor： LAMBRECHT, Frank

IPC: H01L25/10

CPC classification number: H01L23/48 ,  G11C5/025 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/181 ,  H05K2201/097 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611 ,  H01L2924/00

Abstract: The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die.

Abstract translation: 半导体模块包括在衬底的第一侧上的多个存储器管芯和在衬底的第二侧上的多个缓冲管芯。 每个存储器管芯相对设置并电耦合到缓冲管芯之一。

公开(公告)号：WO2007136704A2

公开(公告)日：2007-11-29

申请号：PCT/US2007/011836

申请日：2007-05-17

Applicant: MICRON TECHNOLOGY, INC ,  JIN-MAN, Han

Inventor： JIN-MAN, Han

CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C16/0483 ,  G11C16/12 ,  G11C2207/229

Abstract: The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency.

Abstract translation: 本发明提供了方法和装置。 NAND闪存器件以第一频率接收命令和地址信号，并以大于第一频率的第二频率接收数据信号。

公开(公告)号：WO2004015863A3

公开(公告)日：2004-08-26

申请号：PCT/US0322504

申请日：2003-08-08

Applicant: SUN MICROSYSTEMS INC

Inventor： KLASS EDGARDO F ,  DEMAS ANDREW J

IPC: G11C5/06 ,  G11C7/10 ,  H01L29/00 ,  H04L25/08

CPC classification number: G11C7/1057 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084

Abstract: An interconnect structure (200) includes a signal wire (210) and an' active shield line (220) adjacent to, but removed from, signal wire (210). Interconnect structure (200) also includes another active shield line (230) adjacent to, but removed from, signal wire (210). A signal driver (205) is connected to signal wire (210). Signal driver (205) drives a pulse on signal wire (210). A shield driver (225) is connected to active shield line (220). Shield driver (220) asserts a signal on active shield line (220) substantially simultaneous with the pulse. Another shield driver (235) is connected to another active shield line (230). Another shield driver (235) asserts a signal on another active shield line (230) substantially simultaneous with the pulse. The effect of the simultaneous signals on signal wire (210) and active shield lines (220, 230) is to effectively cancel the lateral capacitances between these lines.

Abstract translation: 互连结构（200）包括与信号线（210）相邻但从信号线（210）移除的信号线（210）和“有源屏蔽线（220）”。 互连结构（200）还包括与信号线（210）相邻但从信号线（210）移除的另一有源屏蔽线（230）。 信号驱动器（205）连接到信号线（210）。 信号驱动器（205）驱动信号线（210）上的脉冲。 屏蔽驱动器（225）连接到主动屏蔽线（220）。 屏蔽驱动器（220）基本上与脉冲同时地在主动屏蔽线（220）上断信号。 另一个屏蔽驱动器（235）连接到另一主动屏蔽线（230）。 另一屏蔽驱动器（235）基本上与脉冲同时地在另一有源屏蔽线（230）上断言信号。 信号线（210）和有源屏蔽线（220,230）上的同时信号的效果是有效地消除这些线之间的横向电容。

公开(公告)号：WO2004015863A2

公开(公告)日：2004-02-19

申请号：PCT/US2003/022504

申请日：2003-08-08

Applicant: SUN MICROSYSTEMS, INC.

Inventor： KLASS, Edgardo, F. ,  DEMAS, Andrew, J.

IPC: H03K

CPC classification number: G11C7/1057 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084

Abstract: An interconnect structure (200) includes a signal wire (210) and an' active shield line (220) adjacent to, but removed from, signal wire (210). Interconnect structure (200) also includes another active shield line (230) adjacent to, but removed from, signal wire (210). A signal driver (205) is connected to signal wire (210). Signal driver (205) drives a pulse on signal wire (210). A shield driver (225) is connected to active shield line (220). Shield driver (220) asserts a signal on active shield line (220) substantially simultaneous with the pulse. Another shield driver (235) is connected to another active shield line (230). Another shield driver (235) asserts a signal on another active shield line (230) substantially simultaneous with the pulse. The effect of the simultaneous signals on signal wire (210) and active shield lines (220, 230) is to effectively cancel the lateral capacitances between these lines.

Abstract translation: 互连结构（200）包括信号线（210）和与信号线（210）相邻但从中移除的“有源屏蔽线（220）”。 互连结构（200）还包括与信号线（210）相邻但从信号线（210）移除的另一有源屏蔽线（230）。 信号驱动器（205）连接到信号线（210）。 信号驱动器（205）在信号线（210）上驱动脉冲。 屏蔽驱动器（225）连接到有源屏蔽线（220）。 屏蔽驱动器（220）基本上与脉冲同时在有源屏蔽线（220）上声明信号。 另一个屏蔽驱动器（235）连接到另一个有源屏蔽线（230）。 另一屏蔽驱动器（235）基本上与脉冲同时在另一有源屏蔽线（230）上断言信号。 信号线（210）和有源屏蔽线（220,230）上的同时信号的作用是有效地消除这些线之间的横向电容。

公开(公告)号：WO02069496A2

公开(公告)日：2002-09-06

申请号：PCT/US0202760

申请日：2002-02-01

Applicant: MICRON TECHNOLOGY INC

Inventor： WRIGHT JEFFREY P ,  WILSON ALAN J

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  H03K5/24

CPC classification number: G11C7/225 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C8/18

Abstract: An integrated circuit clock buffer is described which includes a pulser circuit having a delayed feedback to provide a pulsed signal in response to a transition in the external clock signal. The pulser circuit includes a delay element having an output node coupled to the input node of an inverter. The delay element and inverter are coupled between a first and second transistor. The buffer circuit generates non-skewed internal clock signals.

Abstract translation: 描述了集成电路时钟缓冲器，其包括具有延迟反馈的脉冲发生器电路，以响应于外部时钟信号中的转变来提供脉冲信号。 脉冲发生器电路包括具有耦合到逆变器的输入节点的输出节点的延迟元件。 延迟元件和反相器耦合在第一和第二晶体管之间。 缓冲电路产生非偏斜的内部时钟信号。