公开(公告)号：WO2006039106A1

公开(公告)日：2006-04-13

申请号：PCT/US2005/032770

申请日：2005-09-12

Applicant: RAMBUS INC. ,  WARE, Frederick, A. ,  LAI, Lawrence ,  BELLOWS, Chad, A. ,  RICHARDSON, Wayne, S.

Inventor： WARE, Frederick, A. ,  LAI, Lawrence ,  BELLOWS, Chad, A. ,  RICHARDSON, Wayne, S.

IPC: G11C8/12 ,  G11C8/16

CPC classification number: G11C8/10 ,  G11C8/12 ,  G11C8/16

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address. A second plurality of storage cells in a second row of storage cells in a second bank is accessible in response to a second column address. A third plurality of storage cells in the first row of storage cells is accessible in response to a third column address and a fourth plurality of storage cells in the second row of storage cells is accessible in response to a fourth column address. The first and second column addresses are in a first request packet and the third and fourth column addresses are in a second request packet provided by the master device.

Abstract translation: 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问存储单元行或存储体中的页面。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 在第三操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元中的第一多个存储单元。 响应于第二列地址，可访问第二存储体中第二行存储单元中的第二多个存储单元。 第一行存储单元中的第三多个存储单元响应于第三列地址而可访问，并且第二行存储单元中的第四多个存储单元响应于第四列地址而可访问。 第一列地址和第二列地址在第一请求分组中，并且第三和第四列地址在由主设备提供的第二请求分组中。

公开(公告)号：WO2005026957A3

公开(公告)日：2005-06-23

申请号：PCT/US2004029333

申请日：2004-09-08

Applicant: HEWLETT PACKARD DEVELOPMENT CO ,  KUEKES PHILIP J ,  WILLIAMS R STANLEY ,  SEROUSSI GADIEL

Inventor： KUEKES PHILIP J ,  WILLIAMS R STANLEY ,  SEROUSSI GADIEL

IPC: G06F11/10 ,  G11C8/10 ,  G11C8/20 ,  G11C13/00

CPC classification number: G06F11/1016 ,  B82Y10/00 ,  G11C8/10 ,  G11C13/0014 ,  G11C2213/77 ,  G11C2213/81

Abstract: Methods for increasing defect tolerance and fault tolerance in systems containing interconnected components, in which a signal level is classified as belonging to one of a plurality of different, distinguishable classes based on one or more thresholds separating the signal-level classes, and defect-and-fault tolerant systems embodying the methods. An electronic-device embodiment including an array of nanowire crossbars, the nanoscale memory elements within the nanowire crossbars addressed through conventional microelectronic address lines, and a method embodiment for providing fault-tolerant interconnection interfaces with electrically distinguishable signal levels are described. In the described embodiment, in order to interconnect microelectronic address lines with the nanowire crossbars within the electronic memory, an address encoding technique is employed to generate a number of redundant, parity-check address lines to supplement a minimally required set of address signal lines needed to access the nanoscale memory elements.

Abstract translation: 用于增加包含互连组件的系统中的缺陷容限和容错的方法，其中信号电平基于分离信号电平类别的一个或多个阈值被分类为属于多个不同的可区分类别中的一个，以及缺陷 体现这些方法的容错系统。 包括纳米线交叉杆阵列的电子设备实施例中，纳米线交叉杆内的纳米级的存储元件通过传统的微电子地址线寻址，以及用于提供容错互连接口与电可区别的信号电平的方法实施例进行说明。 在所述实施例中，为了在电子存储器内的互连与所述纳米线交叉杆微电子地址线，一个地址编码技术被利用来产生若干多余的，奇偶校验地址线来补充最低限度所需的一组的地址信号线需要 访问纳米级存储元件。

公开(公告)号：WO2004061859A2

公开(公告)日：2004-07-22

申请号：PCT/US2003/023198

申请日：2003-07-24

Applicant: DEHON, Andre' ,  LIEBER, Charles, M. ,  LINCOLN, Patrick, D. ,  SAVAGE, John

Inventor： DEHON, Andre' ,  LIEBER, Charles, M. ,  LINCOLN, Patrick, D. ,  SAVAGE, John

IPC: G11C13/02

CPC classification number: H01L49/00 ,  B82Y10/00 ,  G11C8/10 ,  G11C13/0023 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/81 ,  H01L23/522 ,  H01L27/101 ,  H01L29/0665 ,  H01L29/0673 ,  H01L2924/0002 ,  Y10S977/762 ,  Y10S977/943 ,  H01L2924/00

Abstract: A method for controlling electric conduction on nanoscale wires is disclosed.The nanoscale wires are provided with controllable regions axially and/or radially distributed. Controlling those regions by means of microscale wires or additional nanoscale wires allows or prevents electric conduction on the controlled nanoscale wires. The controllable regions are of two different types.For example, a first type of controllable region can exhibit a different dopingfrom a second type of controllable region. The method allows one or more of a set of nanoscale wires, packed at sublithographic pitch, to be independentlyselected.

Abstract translation: 公开了一种用于控制纳米尺寸导线上的导电的方法。纳米尺寸线材设有轴向和/或径向分布的可控区域。 通过微细线或额外的纳米线控制这些区域可以允许或防止受控纳米尺寸导线上的电导。 可控区域有两种不同的类型。例如，第一类型的可控区域可以表现出与第二类型可控区域不同的掺杂。 该方法允许独立地选择以亚光刻间距包装的一组纳米级线。

公开(公告)号：WO2003065377A1

公开(公告)日：2003-08-07

申请号：PCT/JP2002/009438

申请日：2002-09-13

Applicant: 株式会社 日立製作所 ,  半澤 悟 ,  伊藤 清男 ,  松岡 秀行 ,  寺尾 元康 ,  阪田 健

Inventor： 半澤 悟 ,  伊藤 清男 ,  松岡 秀行 ,  寺尾 元康 ,  阪田 健

IPC: G11C11/21

CPC classification number: H01L27/101 ,  G11C7/12 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144

Abstract: In a memory array consisting of memory cells using a variable resistance storage element and a selection transistor, when current flows in the selection transistor in all the memory cells on the selection word line, non-selection data line should not be driven. For this, a source line parallel to the data line is provided, a pre-charge circuit is provided for driving the both equipotentially, and a circuit for selectively driving the source line is arranged. With this configuration, it is possible to create a current path and generate a read-out signal only in cells selected by the row and column. Thus, it is possible to realize a non-volatile memory such as a phase-change memory having a high integrity, a low noise, and low power consumption as compared to the conventional one.

Abstract translation: 在由使用可变电阻存储元件和选择晶体管的存储单元组成的存储器阵列中，当选择字线上的所有存储单元中的电流流过选择晶体管时，不应该驱动非选择数据线。 为此，提供与数据线平行的源极线，提供用于等电位驱动的预充电电路，并且布置用于选择性地驱动源极线的电路。 利用这种配置，可以创建一个当前路径，并且仅在由行和列选择的单元格中产生读出信号。 因此，与传统的存储器相比，可以实现诸如具有高完整性，低噪声和低功耗的相变存储器的非易失性存储器。

公开(公告)号：WO2003025938A1

公开(公告)日：2003-03-27

申请号：PCT/US2001/028911

申请日：2001-09-17

Applicant: CASCADE SEMICONDUCTOR CORPORATION ,  CHEN, Wenliang

Inventor： CHEN, Wenliang

IPC: G11C7/00

CPC classification number: G11C11/4087 ,  G11C8/10

Abstract: An improved memory device employs a DRAM array for data storage. In the device, a special row address decoder (74, 76) simultaneously asserts a corresponding unique pair of the wordlines (62, 64) in response to each received valid row address, so that a single valid row address simultaneously accesses two rows of memory cells in the array. The device differentially writes and reads each bit of data across a pair of memory cells; each one of the pair of memory cells being within a different respective row of the array, and the two different rows together corresponding to one of the unique pairs of wordlines asserted by the row address decoder responsive to a valid row address. This arrangement obviates the need for high voltage boosting circuits and thereby reduces power consumption.

Abstract translation: 改进的存储器件采用用于数据存储的DRAM阵列。 在设备中，响应于每个接收到的有效行地址，特殊的行地址解码器（74,76）同时断言对应的唯一的字线对（62,64），使得单个有效行地址同时访问两行存储器 阵列中的单元格。 该器件通过一对存储器单元差分地写入和读取数据的每一位; 所述一对存储单元中的每一个位于所述阵列的不同的相应行内，并且所述两个不同的行一起对应于由所述行地址解码器响应于有效行地址所确定的唯一的字对对之一。 这种布置避免了对高压升压电路的需要，从而降低功耗。

公开(公告)号：WO0115171A3

公开(公告)日：2002-09-12

申请号：PCT/US0019303

申请日：2000-07-14

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BILL COLIN S ,  SU JOHATHAN SHI-CHANG ,  GUTALA RAVI P

IPC: G11C16/06 ,  G11C8/10 ,  G11C8/12 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C8/00 ,  G11C16/08

CPC classification number: G11C8/12 ,  G11C8/10

Abstract: The present invention discloses a memory wordline decoder that includes plurality of pre-decoded address lines that are electrically connected with a global x-decoder. A sub x-decoder is electrically connected with the global x-decoder for receiving electrical control signals from the global x-decoder. A memory sector is electrically connected with the sub x-decoder. The global x-decoder selectively controls the sub x-decoder to select a plurality of wordlines in the memory sector. A vertical x-decoder is electrically connected with the global x-decoder and the sub x-decoder. The vertical x-decoder is used to select a predetermined wordline by the global x-decoder during operation.

Abstract translation: 本发明公开了一种存储器字线解码器，其包括与全局x-解码器电连接的多个预解码地址线。 子x解码器与全局x解码器电连接，用于从全局x解码器接收电控信号。 存储器扇区与子x-解码器电连接。 全局x解码器选择性地控制子x解码器以选择存储器扇区中的多个字线。 垂直x解码器与全局x解码器和子x解码器电连接。 垂直x解码器用于在操作期间由全局x解码器选择预定字线。

公开(公告)号：WO0152265A2

公开(公告)日：2001-07-19

申请号：PCT/GB0100116

申请日：2001-01-12

Applicant: ELEMENT 14 INC ,  BEAT ROBERT

Inventor： BEAT ROBERT

IPC: G11C8/10 ,  G11C11/418 ,  G11C11/00

CPC classification number: G11C11/418 ,  G11C8/10

Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential; and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the second decode node to a discharging potential; and second selection circuitry coupled to a respective one of the output lines and operable in response to a second enable signal to select that output line if the second discharge node has not discharged; wherein the first enable signal is derived from the potential of the second decode node.

Abstract translation: 一种解码电路，用于根据多条输入线的状态选择多条输出线中的一条输出线，该电路包括：第一解码装置，包括：第一解码节点; 第一预充电电路，用于将第一解码节点充电到充电电位; 第一放电电路，其包括多个切换装置，每个切换装置都可以根据各条输入线的状态进行操作，以将第一解码节点耦合到放电电位; 以及第一选择电路，其耦合到所述输出线中的相应一者，并且可响应于第一启用信号而操作以在所述第一解码节点未放电的情况下选择所述输出线; 以及第二解码装置，包括：第二解码节点; 第二预充电电路，用于将第二解码节点充电至充电电位; 第二放电电路，其包括多个开关装置，每个开关装置都可以根据各个输入线的状态进行操作，以将第二解码节点耦合到放电电位; 以及第二选择电路，其耦合到所述输出线中的相应输出线并且可响应于第二使能信号而操作以在所述第二放电节点未放电的情况下选择所述输出线; 其中所述第一使能信号是从所述第二解码节点的电位导出的。

公开(公告)号：WO0031729A8

公开(公告)日：2000-10-12

申请号：PCT/SE9902147

申请日：1999-11-23

Applicant: PRIQUEUE AB ,  MUNRO JAMES IAN ,  BRODNIK ANDREJ ,  CARLSSON SVANTE

Inventor： MUNRO JAMES IAN ,  BRODNIK ANDREJ ,  CARLSSON SVANTE

IPC: G06F12/00 ,  G11C7/10 ,  G11C8/10 ,  G11C5/00 ,  G06F12/08 ,  G06F17/30

CPC classification number: G11C7/1006 ,  G11C8/10

Abstract: A digital memory structure manages a subset N of a universe U = {0...M-1} of elements e, where the universe U is represented by a complete binary tree of height m+1 with elements e of the universe U at its leaves. The digital memory structure has an array of overlapped registers reg[i], preferably where 0 )+ 2 ). Any internal node of the binary tree is stored as tagged, if the right and/or the left subtree thereof contain(s) at least one element of subset N. The digital memory structure also has an array of pointers internal[1], preferably where 1

Abstract translation: 数字存储器结构管理元素e的宇宙U = {0 ... M-1}的子集N，其中宇宙U由高度m + 1的完整二叉树表示，其中宇宙U的元素e在 它的叶子。 数字存储器结构具有重叠寄存器寄存器reg [i]的阵列，优选地，其中0 ）+ 2 ）。 二叉树的任何内部节点都被存储为标记，如果右侧和/或左侧子树包含子集N的至少一个元素。数字存储器结构还具有内部[1]的指针阵列，优选地 对于每个相应的内部节点1，其中1