公开(公告)号：WO2019055105A1

公开(公告)日：2019-03-21

申请号：PCT/US2018/040811

申请日：2018-07-03

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： TIWARI, Vipin ,  DO, Nhan

IPC: G11C7/06 ,  G11C16/24

Abstract: A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output. For each of the differential sense amplifiers, the differential sense amplifier is configured to generate an output signal on the output having an amplitude that is based upon a difference in signal amplitudes on the first and second inputs, the first input is connected to one of the bit lines, and the second input is connected to another one of the bit lines. Alternately, one or more sense amplifiers are configured to detect signal amplitudes on the bit lines, and the device includes calculation circuitry configured to produce output signals each based upon a difference in signal amplitudes on two of the bit lines.

公开(公告)号：WO2017200850A1

公开(公告)日：2017-11-23

申请号：PCT/US2017/032280

申请日：2017-05-11

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： TRAN, Hieu Van ,  TIWARI, Vipin ,  DO, Nhan

IPC: H01L27/04 ,  H01L27/115 ,  H01L27/1159

Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

Abstract translation: 包括半导体材料的衬底和形成在衬底上并且以行和列的阵列布置的多个存储器单元的存储器件和擦除存储器件的方法。 每个存储器单元包括在衬底中的间隔开的源极区和漏极区，衬底中的沟道区在其间延伸，设置在与源极区相邻的沟道区的第一部分之上并与之绝缘的浮置栅极， 选择栅极，设置在与漏极区域相邻的沟道区域的第二部分之上并与其绝缘;以及编程擦除栅极，设置在源极区域之上并与其绝缘。 编程擦除栅极线单独或与选择栅极线或源极线组合在列方向上排列，使得每个存储器单元可以被单独编程，读取和擦除。

公开(公告)号：WO2017065938A1

公开(公告)日：2017-04-20

申请号：PCT/US2016/052517

申请日：2016-09-19

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： KIM, Jinho ,  SU, Chien-sheng ,  ZHOU, Feng ,  LIU, Xian ,  DO, Nhan ,  TUNTASOOD, Prateep ,  GHAZAVI, Parviz

IPC: H01L21/02 ,  H01L21/8229 ,  H01L21/8239

CPC classification number: H01L27/11531 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.

Abstract translation: 在具有存储器，核心和HV器件区域的衬底上形成存储器件的方法。 该方法包括在所有三个区域中形成一对导电层，在所有三个区域中的导电层上方形成绝缘层（以保护核心和HV器件区域），然后通过绝缘层和一对导电层 在内存区域形成内存堆栈。 该方法进一步包括在存储器堆叠上方形成绝缘层（以保护存储器区域），去除核心和HV器件区域中的一对导电层，以及在核心中形成设置在衬底上并与之绝缘的导电栅极，并且HV 设备区域。

公开(公告)号：WO2016148873A1

公开(公告)日：2016-09-22

申请号：PCT/US2016/019860

申请日：2016-02-26

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： SU, Chien-Sheng ,  YANG, Jeng-Wei ,  WU, Man-Tang ,  TRAN, Hieu Van ,  DO, Nhan ,  CHEN, Chun-Ming

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

Abstract: A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

Abstract translation: 一种非易失性存储单元，包括具有上表面和两个侧表面的鳍形上表面的半导体衬底。 源极和漏极区域形成在鳍状上表面部分中，其间具有沟道区域。 导电浮栅包括沿着顶表面的第一部分延伸的第一部分，以及分别沿两个侧表面的第一部分延伸的第二和第三部分。 导电控制栅极包括沿着顶表面的第二部分延伸的第一部分，分别沿着两个侧表面的第二部分延伸的第二部分和第三部分，第一部分和第二部分， 以及分别延伸至少一些所述浮动栅极第二和第三部分的第五和第六部分。

公开(公告)号：WO2016089544A1

公开(公告)日：2016-06-09

申请号：PCT/US2015/059407

申请日：2015-11-06

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： ZHOU, Feng ,  LIU, Xian ,  DO, Nhan

IPC: H01L29/423 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

Abstract: A memory cell includes source and drain regions in a substrate with a channel region therebetween, an erase gate over the source region, a floating gate over a first channel region portion, a control gate over the floating gate, and a wordline gate over a second channel region portion. A first logic device includes second source and drain regions in the substrate with a second channel region therebetween under a first logic gate. A second logic device includes third source and drain regions in the substrate with a third channel region therebetween under a second logic gate. The wordline gate and the first and second logic gates comprise the same conductive metal material. The second logic gate is insulated from the third channel region by first and second insulation. The first logic gate is insulated from the second channel region by the second insulation and not by the first insulation.

Abstract translation: 存储单元包括在其中具有沟道区域的衬底中的源极和漏极区域，源极区域上的擦除栅极，在第一沟道区域部分上的浮动栅极，浮置栅极上的控制栅极以及第二沟道区域上的字线栅极 通道区域部分。 第一逻辑器件包括衬底中的第二源极和漏极区域，在第一逻辑门之下具有第二沟道区域。 第二逻辑器件包括衬底中的第三源极和漏极区域，在第二逻辑门极之间具有第三沟道区域。 字线栅极和第一和第二逻辑门包括相同的导电金属材料。 第二逻辑门通过第一和第二绝缘与第三沟道区绝缘。 第一逻辑门通过第二绝缘而与第二沟道区绝缘，而不是通过第一绝缘。

公开(公告)号：WO2015112282A1

公开(公告)日：2015-07-30

申请号：PCT/US2014/070674

申请日：2014-12-16

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： YANG, Jeng-Wei ,  SU, Chien-Sheng

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L21/3088

Abstract: A method of forming active areas and isolation regions in a semiconductor substrate using a double patterning process. The method include forming a first material on the substrate surface, forming a second material on the first material, forming a plurality of first trenches into the second material wherein the plurality of first trenches are parallel to each other, forming a second trench into the second material wherein the second trench is perpendicular to and crosses the plurality of first trenches in a central region of the substrate, filling the first and second trenches with a third material, removing the second material to form third trenches in the third material that are parallel to each other and do not extend through the central region of the substrate, and extending the third trenches through the first material and into the substrate.

Abstract translation: 使用双重图案化工艺在半导体衬底中形成有源区和隔离区的方法。 该方法包括在衬底表面上形成第一材料，在第一材料上形成第二材料，在第二材料中形成多个第一沟槽，其中多个第一沟槽彼此平行，形成第二沟槽 材料，其中所述第二沟槽在所述衬底的中心区域中垂直于所述第一沟槽并与所述多个第一沟槽交叉，用第三材料填充所述第一和第二沟槽，移除所述第二材料以在所述第三材料中形成平行于所述第三材料的第三沟槽 彼此不延伸穿过衬底的中心区域，并且延伸第三沟槽穿过第一材料并进入衬底。

公开(公告)号：WO2015112278A1

公开(公告)日：2015-07-30

申请号：PCT/US2014/070262

申请日：2014-12-15

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： DO, Nhan

IPC: G11C16/04

CPC classification number: G11C16/14 ,  G11C5/063 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/16 ,  H01L27/11519 ,  H01L27/11521

Abstract: Memory cells arranged in rows and columns, each with source and drain regions of equal breakdown voltages, and floating and control gates over the channel region. The memory cell rows are arranged in clusters each with a source line connecting all the source regions in just that cluster. Word lines each connect all the control gates for a row of memory cells. Bit lines each connect all the drain regions for a column of memory cells. Source line interconnects each connect all the source lines for a column of clusters. One cluster is erased by applying a positive voltage to a word line for that cluster and ground potential to other word lines, ground potential to the source line interconnect for that cluster and a positive voltage to other source line interconnects, and ground potential to the bit lines for that cluster and a positive voltage to other bit lines.

Abstract translation: 排列成行和列的存储单元，每个具有相同击穿电压的源极和漏极区域，以及在沟道区域上的浮动和控制栅极。 存储单元行被排列成簇，每个簇具有连接所述簇中的所有源区的源极线。 字线各连接一行存储单元的所有控制门。 位线每个连接一列存储单元的所有漏极区域。 源线互连每个连接一个集群列的所有源线。 通过向该簇的字线施加正电压并将其与其他字线的接地电位，对于该集群的源极线互连的接地电位和对其它源极线互连的正电压以及对该位的接地电位，将一个集群擦除 该群集的线路和其他位线的正电压。

公开(公告)号：WO2015094730A1

公开(公告)日：2015-06-25

申请号：PCT/US2014/069002

申请日：2014-12-08

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： CHEN, Bomy ,  SU, Chien-sheng ,  DO, Nhan

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/42328 ,  G11C16/0408 ,  G11C16/10 ,  H01L21/28238 ,  H01L27/11517 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

Abstract: A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. The control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. The erase gate is disposed at least partially over and insulated from the floating gate. Any portion of the trench between the pair of floating gates is free of electrically conductive elements except for a lower portion of the erase gate.

Abstract translation: 存储器件及其制造方法，其中将沟槽形成为半导体材料的衬底。 源极区形成在沟槽下方，并且源极和漏极区域之间的沟道区域包括基本上沿着沟槽的侧壁延伸的第一部分和基本上沿着衬底的表面延伸的第二部分。 浮栅设置在沟槽中，与沟道区第一部分绝缘，以控制其导电性。 控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘，以控制其导电性。 擦除栅极至少部分地布置在浮栅上并与浮栅绝缘。 一对浮动栅极之间的沟槽的任何部分除了擦除栅极的下部之外没有导电元件。

公开(公告)号：WO2014194277A1

公开(公告)日：2014-12-04

申请号：PCT/US2014/040364

申请日：2014-05-30

Applicant: 1020, INC.

Inventor： BEZANCON, Anne ,  PARKES, Daniel

IPC: G06Q20/00

CPC classification number: G06Q20/4016 ,  G06Q20/20 ,  G06Q20/3224 ,  G06Q20/405 ,  G06Q20/409

Abstract: A system and method for authorizing a transaction that includes a transaction device configured to send over a network information relating to a transaction and a commerce card and a transaction processing device configured to receive over the network the information sent by the transaction device and information sent from a mobile device associated with the commerce card. The transaction processing device is configured to authorize the transaction based on the information received from the transaction device and the information received from the mobile device. The transaction processing device can also authorize the transaction at last in part on criteria associated with the commerce card.

Abstract translation: 一种用于授权交易的系统和方法，所述交易包括被配置为通过网络发送与交易和商务卡有关的信息的交易设备和交易处理设备，该交易处理设备被配置为经由网络接收由交易设备发送的信息和从 与商务卡相关联的移动设备。 交易处理装置被配置为基于从交易设备接收的信息和从移动设备接收的信息来授权交易。 事务处理设备还可以最后部分地基于与商务卡相关联的标准来授权交易。

公开(公告)号：WO2014062435A1

公开(公告)日：2014-04-24

申请号：PCT/US2013/064013

申请日：2013-10-09

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： TRAN, Hieu, Van ,  LY, Anh ,  VU, Thuan ,  NGUYEN, Hung, Quoc

IPC: G11C16/10 ,  G11C16/08 ,  G11C8/08 ,  G11C5/14 ,  G11C11/56

CPC classification number: G11C5/145 ,  G11C8/08 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10

Abstract: A non-volatile memory device that includes N planes (102a, 102b) of non-volatile memory cells (where N is an integer greater than 1). Each plane of non-volatile memory cells (10) includes a plurality of memory cells configured in rows (22) and columns (20). Each of the N planes includes gate lines (26, 14, 28) that extend across the rows of the memory cells therein but do not extend to others of the N planes of non-volatile memory cells. A controller is configured to divide each of a plurality of words of data into N fractional-words, and program each of the N fractional-words of each word of data into a different one of the N planes of non-volatile memory cells. The controller uses a programming current and a program time period for the programming, and can be configured to vary the programming current by a factor and inversely vary the program time period by the factor.

Abstract translation: 一种非易失性存储器件，其包括非易失性存储器单元的N个平面（102a，102b）（其中N是大于1的整数）。 非易失性存储单元（10）的每个平面包括以行（22）和列（20）配置的多个存储单元。 N平面中的每一个包括跨越其中的存储单元的行延伸但不延伸到非易失性存储单元的N个平面中的其他平面的栅极线（26,14,28）。 控制器被配置为将多个数据字中的每一个分成N个小数字，并且将每个数据字的N个分数字中的每一个分解成非易失性存储单元的N个平面中的不同的一个。 控制器使用编程电流和编程时间段进行编程，并且可以配置为通过一个因素改变编程电流，并通过因子反向改变程序时间段。