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    不揮発性半導体記憶装置およびその製造方法
    71.
    发明申请
    不揮発性半導体記憶装置およびその製造方法 审中-公开
    非易失性半导体存储器件及其制造方法

    公开(公告)号：WO2006132158A1

    公开(公告)日：2006-12-14

    申请号：PCT/JP2006/311122

    申请日：2006-06-02

    Applicant: シャープ株式会社 ,  舛岡 富士雄 ,  大場 卓也

    Inventor： 舛岡 富士雄 ,  大場 卓也

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L29/66825

    Abstract: 　浮遊ゲート及び制御ゲートを有する半導体記憶装置の、占有面積を増加させずに浮遊ゲートと制御ゲートとの容量の比をより一層増大させる半導体記憶装置及びその製造方法を提供することを目的とする。 　半導体層の側壁の周囲の全部に形成された浮遊ゲート及び制御ゲートから構成されるメモリセルを有する半導体記憶装置であり、浮遊ゲートを半導体層の底部から離すことにより、制御ゲートを浮遊ゲート下部に形成する。さらに、浮遊ゲート上部に制御ゲートを形成することにより、凹形状の制御ゲートを作る手段を提供する。

    Abstract translation: 提供一种半导体存储装置，其中提供浮动栅极和控制栅极，并且在不增加器件的占用面积的情况下进一步增加浮动栅极和控制栅极之间的电容率，以及制造这种半导体存储器的方法 设备。 半导体存储装置具有由半导体层的侧壁的圆周上完全形成的浮栅和控制栅极构成的存储单元。 控制栅极通过从浮动栅极与半导体层的底部分离来形成在浮栅之下。 此外，提供了一种用于通过在浮动栅极上形成控制栅极来形成具有凹陷形状的控制栅极的装置。

    PROGRAMMING AND ERASING STRUCTURE FOR A FLOATING GATE MEMORY CELL AND METHOD OF MAKING
    72.
    发明申请
    PROGRAMMING AND ERASING STRUCTURE FOR A FLOATING GATE MEMORY CELL AND METHOD OF MAKING 审中-公开
    浮动门存储单元的编程和擦除结构及其制作方法

    公开(公告)号：WO2006036334A2

    公开(公告)日：2006-04-06

    申请号：PCT/US2005/028828

    申请日：2005-08-15

    Applicant: FREESCALE SEMICONDUCTOR, INC. ,  CHINDALORE, Gowrishankar, L. ,  SWIFT, Craig, T.

    Inventor： CHINDALORE, Gowrishankar, L. ,  SWIFT, Craig, T.

    IPC: H01L21/336

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

    Abstract: A floating gate memory cell (10) has a floating gate in which there are two floating gate layers (18, 22). The top layer (22) is etched to provide a contour in the top layer (22) while leaving the lower layer (18) unchanged. The control gate (38) follows the contour of the floating gate (22) to increase capacitance therebetween. The two layers (18, 22) of the floating gate can be polysilicon separated by a very thin etch stop layer (20). This etch stop layer (20) is thick enough to provide an etch stop during a polysilicon etch but preferably thin enough to be electrically transparent. Electrons are able to easily move between the two layers (22, 18). Thus the etch of the top layer (22) does not extend into the lower layer (18) but the first (18) and second layer (22) have the electrical effect for the purposes of a floating gate of being a continuous conductive layer.

    Abstract translation: 浮动栅极存储单元（10）具有浮置栅极，其中存在两个浮置栅极层（18,22）。 蚀刻顶层（22）以在顶层（22）中提供轮廓，同时使下层（18）保持不变。 控制栅极（38）跟随浮动栅极（22）的轮廓，以增加它们之间的电容。 浮栅的两层（18,22）可以是由非常薄的蚀刻停止层（20）分离的多晶硅。 该蚀刻停止层（20）足够厚以在多晶硅蚀刻期间提供蚀刻停止，但优选足够薄以使其具有电透性。 电子能够容易地在两层（22,18）之间移动。 因此，顶层（22）的蚀刻不延伸到下层（18）中，但是为了作为连续导电层的浮动栅极的目的，第一层（18）和第二层（22）具有电效应。

    FLOATING GATE MEMORY CELLS WITH INCREASED COUPLING RATIO
    73.
    发明申请
    FLOATING GATE MEMORY CELLS WITH INCREASED COUPLING RATIO 审中-公开
    具有增加的耦合比的浮栅存储器电池

    公开(公告)号：WO2003096431A1

    公开(公告)日：2003-11-20

    申请号：PCT/IB2003/001485

    申请日：2003-04-11

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  VAN DUUREN, Michiel, J. ,  VAN SCHAIJK, Robertus, T., F.

    Inventor： VAN DUUREN, Michiel, J. ,  VAN SCHAIJK, Robertus, T., F.

    IPC: H01L29/788

    CPC classification number: H01L29/7881 ,  H01L29/42324

    Abstract: A method to improve the coupling ratio between a control gate (18) and a floating gate (14) of a floating gate non-volatile semiconductor device is described. In a stacked gate floating gate transistor according to the invention, a conductive spacer (24) is used at both sides of the stack. The conductive spacer (24) is galvanically connected to the control gate (18), preferably by means of a conductive layer (34), whereas it is separated from the floating gate (14) by means of an insulating layer (22). The capacitance (C1, C2) between both conductive spacers (24) and the side walls of the floating gate (14) adds up to the normal capacitance between control gate (18) and floating gate (14).

    Abstract translation: 描述了一种改善浮动栅极非易失性半导体器件的控制栅极（18）和浮动栅极（14）之间的耦合比的方法。 在根据本发明的堆叠栅极浮栅晶体管中，在堆叠的两侧使用导电间隔物（24）。 导电间隔物（24）优选通过导电层（34）电连接到控制栅极（18），而通过绝缘层（22）与导电间隔物（24）分离。 两个导电间隔物（24）和浮动栅极（14）的侧壁之间的电容（C1，C2）与控制栅极（18）和浮动栅极（14）之间的正常电容相加。

    SELF-ALIGNED NON-VOLATILE MEMORY CELL
    74.
    发明申请
    SELF-ALIGNED NON-VOLATILE MEMORY CELL 审中-公开
    自对准的非易失性记忆细胞

    公开(公告)号：WO0245176B1

    公开(公告)日：2002-08-22

    申请号：PCT/US0132157

    申请日：2001-10-15

    Applicant: ATMEL CORP

    Inventor： LOJEK BOHUMIL ,  RENNINGER ALAN L

    IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L21/76895 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7883

    Abstract: Disclosed is a self-aligned non-volatile memory cell (200) comprising a small sidewall spacer (239) electrically coupled and being located next to a main floating gate region (212). Both the small sidewall spacer (239) and the main floating gate region (212) are formed on a substrate (204) and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer (232) which is thinner (260) between the small sidewall spacer (239) and the substrate (204); and is thicker (263) between the main floating gate region (212) and the substrate (204). The small sidewall spacer (239) can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

    Abstract translation: 公开了一种自对准非易失性存储单元（200），其包括电耦合并位于主浮动栅极区域（212）旁边的小侧壁间隔物（239）。 小侧壁间隔物（239）和主浮栅区（212）都形成在衬底（204）上，并且都形成非易失性存储单元的浮动栅极。 两者通过在小侧壁间隔物（239）和衬底（204）之间较薄（260）的氧化物层（232）与衬底电隔离; 并且在主浮栅区域（212）和衬底（204）之间较厚（263）。 可以使小的侧壁间隔件（239）变小; 因此，也可以使薄的氧化物层面积变小以产生电子隧道进入浮动栅极的小路径。

    VERTICAL CHANNEL FLOATING GATE TRANSISTOR HAVING SILICON GERMANIUM CHANNEL LAYER
    76.
    发明申请
    VERTICAL CHANNEL FLOATING GATE TRANSISTOR HAVING SILICON GERMANIUM CHANNEL LAYER 审中-公开
    具有硅锗通道层的垂直通道浮动栅极晶体管

    公开(公告)号：WO01097292A1

    公开(公告)日：2001-12-20

    申请号：PCT/US2001/019273

    申请日：2001-06-15

    IPC: H01L29/423 ,  H01L29/788

    CPC classification number: H01L29/7885 ,  H01L29/42324

    Abstract: A vertical channel flash memory cell with a silicon germanium layer (24) in the channel region provides enhanced secondary electron injection when programming the device. The device includes a silicon substrate (10), a silicon germanium alloy layer (24) epitaxially grown on the substrate, and a silicon layer (260) epitaxially grown on the silicon germanium layer. A sidewall through the stacked structure is formed by etching thereby exposing edges of the silicon layer and the silicon germanium layer and a portion of the substrate. A floating gate (18) is formed overlying the sidewall and insulated therefrom with a control gate (20) overlying the floating gate and insulated therefrom. A source region (14) is formed in the silicon layer and a drain region (12) is formed in the substrate with a channel therebetween along the sidewall and including the silicon germanium layer. The silicon germanium layer (24) is preferably compressively strained and can have a uniform mole fraction or a graded mole fraction. The vertical structure permits the fabrication of flash memory cells with smaller dimensions and lower operating voltages.

    Abstract translation: 在通道区域中具有硅锗层（24）的垂直通道闪速存储器单元在编程器件时提供增强的二次电子注入。 该器件包括硅衬底（10），在衬底上外延生长的硅锗合金层（24）和在硅锗层上外延生长的硅层（260）。 通过蚀刻形成通过层叠结构的侧壁，从而暴露硅层和硅锗层的边缘以及衬底的一部分。 浮动栅极（18）形成为覆盖在侧壁上并与其上方的与浮动栅极重叠并与之隔绝的控制栅极（20）绝缘。 源极区（14）形成在硅层中，并且漏极区（12）形成在衬底中，沿着侧壁具有沟道，并且包括硅锗层。 硅锗层（24）优选地被压缩应变，并且可以具有均匀的摩尔分数或分级摩尔分数。 垂直结构允许制造具有较小尺寸和较低工作电压的闪存单元。

    MEMORY CELL WITH SELF-ALIGNED FLOATING GATE AND SEPARATE SELECT GATE, AND FABRICATION PROCESS
    78.
    发明申请
    MEMORY CELL WITH SELF-ALIGNED FLOATING GATE AND SEPARATE SELECT GATE, AND FABRICATION PROCESS 审中-公开
    具有自对准浮动门和独立选择门和制造工艺的存储单元

    公开(公告)号：WO01011691A1

    公开(公告)日：2001-02-15

    申请号：PCT/US2000/020235

    申请日：2000-07-26

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328

    Abstract: Memory cell having a floating gate (41) with lateral edges (41a, 41b) which are aligned directly above edges (42a), (42b) of the active area (42) in the substrate (46), a control gate (43) positioned directly above the floating gate (41), and a select gate (44) spaced laterally from the control gate (43). The memory cell is fabricated by forming a poly-1 layer and an overlying dielectric film on a substrate in areas in which the stack transistors are to be formed, forming a poly-2 layer over the dielectric film and over areas of the substrate in which the select transistors are to be formed, patterning the poly-2 layer to form control gates for the stack transistors and select gates for the select transistors, removing the poly-1 layer and the dielectric film to form floating gates in areas which are not covered by the control gates, and forming source and drain regions in the substrate.

    Abstract translation: 具有横向边缘（41a，41b）的浮动栅极（41）的存储单元，其直接对准衬底（46）中的有源区域（42）的边缘（42a），（42b）上方，控制栅极（43） 位于浮动栅极（41）正上方，以及与控制栅极（43）横向间隔开的选择栅极（44）。 通过在要形成堆叠晶体管的区域中在衬底上形成多晶硅层和覆盖电介质膜来制造存储器单元，在电介质膜上形成多晶硅层，并在基底的区域 要形成选择晶体管，对多晶硅层进行构图以形成堆叠晶体管的控制栅极和用于选择晶体管的选择栅极，去除多晶硅层和电介质膜，以在未被覆盖的区域中形成浮栅 并且在衬底中形成源区和漏区。

    NONVOLATILE MEMORY
    79.
    发明申请
    NONVOLATILE MEMORY 审中-公开
    非易失性存储器

    公开(公告)号：WO00028597A1

    公开(公告)日：2000-05-18

    申请号：PCT/US1999/024272

    申请日：1999-10-19

    IPC: G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/115 ,  G11C16/0425 ,  G11C16/0433 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885

    Abstract: A nonvolatile memory cell (10a, 10b) which is highly scalable includes a cell formed in a triple well (44, 46). A pair of sources (32, 34) for a pair of cells on adjacent word lines (36) each acts as the emitter of a lateral bipolar transistor (68). The lateral bipolar transistor (68) of one cell (10) operates as a charge injector for the other cell (10). The charge injector provides carriers for substrate hot carrier injection onto a floating gate (28b).

    Abstract translation: 高度可缩放的非易失性存储单元（10a，10b）包括形成在三阱（44,46）中的单元。 用于相邻字线（36）上的一对单元的一对源（32,34）各自用作横向双极晶体管（68）的发射极。 一个电池（10）的横向双极晶体管（68）作为另一个电池（10）的电荷注入器工作。 电荷注入器提供用于衬底热载流子注入到浮动栅极（28b）上的载体。

    NOVEL MULTI-STATE MEMORY
    80.
    发明申请
    NOVEL MULTI-STATE MEMORY 审中-公开
    新的多状态存储器

    公开(公告)号：WO99008284A2

    公开(公告)日：1999-02-18

    申请号：PCT/US1998/015657

    申请日：1998-07-29

    IPC: G11C16/02 ,  G11C11/56 ,  G11C27/00 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  G11C11/00

    CPC classification number: H01L27/115 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0425 ,  G11C16/0441 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/349 ,  G11C16/3495 ,  G11C27/005 ,  G11C29/00 ,  G11C29/76 ,  G11C2211/5634 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885

    Abstract: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

    Abstract translation: 通过灵活，自我一致和自适应的检测方式实现了最大化的多状态压缩和更多的记忆状态容忍度，涵盖了广泛的动态范围。 对于高密度多态编码，这种方法接近完全模拟处理，决定了模拟技术，包括A到D型转换，以重构和处理数据。 根据本发明的教导，以高保真度读取存储器阵列，而不是提供实际的最终数字数据，而是提供准确地反映模拟存储状态的原始数据，哪些信息被发送到存储器控制器用于分析和 检测实际的最终数字数据。

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