公开(公告)号：WO2019133221A2

公开(公告)日：2019-07-04

申请号：PCT/US2018/064423

申请日：2018-12-07

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： SHEN, Dongna ,  WANG, Yu-Jen

Abstract: A process flow for forming magnetic tunnel junctions (MTJs) with minimal sidewall residue and reduced low tail population is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask pattern is etch transferred through the underlying MTJ layers including a reference layer/tunnel barrier/free layer stack. The etch transfer may be completed in a single RIE step based on a first flow rate of O 2 and a second flow rate of an oxidant such as CH 3 OH where the CH 3 OH/O 2 ratio is at least 7.5:1. The RIE may also include a flow rate of a noble gas. In other embodiments, a chemical treatment with an oxidant such as CH 3 OH, and a volatilization at 50°C to 450°C may follow an etch transfer through the MTJ stack when the ion beam etch or plasma etch involves noble gas ions.

公开(公告)号：WO2018213107A1

公开(公告)日：2018-11-22

申请号：PCT/US2018/032196

申请日：2018-05-11

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： SHEN, Dongna ,  WANG, Yu-Jen ,  TONG, Ru-Ying ,  SUNDAR, Vignesh ,  PATEL, Sahil

IPC: H01L43/12

Abstract: Processes for forming magnetic tunnel junction (MTJ) nanopillars (la) with minimal sidewall residue and damage are disclosed wherein a pattern is first formed in a hard mask (15) that is an uppermost MTJ layer. Thereafter, the hard mask sidewall (20) is etch transferred through the remaining MTJ layers including a tunnel barrier (13) between a free layer (14) and a reference layer (12). The etching may be completed in a single RIE step (32m) that features a physical component involving inert gas ions or plasma, and a chemical component comprised of ions or plasma generated from one or more of methanol, ethanol, ammonia, and carbon monoxide. Alternatively, a chemical treatment (33) with one of the aforementioned chemicals, and a volatilization step (34v) may follow MTJ stack patterning using an ion beam etch or RIE involving inert gas ions (32i).

公开(公告)号：WO2018175095A1

公开(公告)日：2018-09-27

申请号：PCT/US2018/020854

申请日：2018-03-05

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： TENG, Zhongjian ,  ZHONG, Tom ,  HAQ, Jesmin

IPC: H01L43/12

Abstract: The proposed method for patterning a magnetic tunneling junction (MTJ) structure comprises providing a patterned mask (18) on a MTJ layer stack (16) formed over a bottom electrode (12) on a wafer (10), etching the stack to form a MTJ device, and removing sidewall damage (22) on the MTJ device by a physical treatment, preferably by using a slurry (27, 47) in a CMP or ultrasonic cleaning tool which physically attacks and removes the sidewall damage.

公开(公告)号：WO2018175089A1

公开(公告)日：2018-09-27

申请号：PCT/US2018/020594

申请日：2018-03-02

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： YI, Yang ,  SHEN, Dongna ,  WANG, Yu-jen

IPC: H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  G11B5/31

Abstract: A stack of MTJ layers is provided on a substrate comprising a bottom electrode, a pinned layer, a tunnel barrier layer, a free layer, and a top electrode. The MTJ stack is patterned to form a MTJ device wherein sidewall damage is formed on its sidewalls. A dielectric spacer is formed on the MTJ device. The dielectric spacer is etched away on horizontal surfaces wherein the dielectric spacer on the sidewalls is partially etched away. The remaining dielectric spacer covers the pinned layer and bottom electrode. The dielectric spacer is removed from the free layer or is thinner on the free layer than on the pinned layer and bottom electrode. Sidewall damage is thereafter removed from the free layer by applying a horizontal etching to the MTJ device wherein the pinned layer and bottom electrode are protected from etching by the dielectric spacer layer.

公开(公告)号：WO2018169676A1

公开(公告)日：2018-09-20

申请号：PCT/US2018/019841

申请日：2018-02-27

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： IWATA, Jodi Mari ,  JAN, Guenole ,  TONG, Ru-Ying ,  WANG, Po-Kang

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, metal clusters are formed in the FL and are subsequently partially or fully oxidized by scavenging oxygen to generate additional FL/oxide interfaces that enhance PMA, provide an acceptable resistance x area (RA) value, and preserve the magnetoresistive ratio. In other embodiments, a continuous or discontinuous metal (M) or MQ alloy layer within the FL reacts with scavenged oxygen to form a partially oxidized metal or alloy layer that enhances PMA and maintains acceptable RA. M is one of Mg, Al, B, Ca, Ba, Sr, Ta, Si, Mn, Ti, Zr, or Hf, and Q is a transition metal, B, C, or Al.

公开(公告)号：WO2016160578A1

公开(公告)日：2016-10-06

申请号：PCT/US2016/024236

申请日：2016-03-25

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： JAN, Guenole ,  WANG, Po-Kang ,  LEE, Yuan-Jen ,  ZHU, Jian ,  LIU, Huanlong

IPC: G11C17/16

CPC classification number: G11C17/18 ,  G11C11/005 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/409 ,  G11C11/419 ,  G11C17/02 ,  G11C17/16 ,  G11C2213/71 ,  H01L27/228 ,  H01L43/12

Abstract: An integrated circuit includes a magnetic OTP memory array formed of multiple magnetic OTP memory cells having an MTJ stack with a fixed magnetic layer, a tunnel barrier insulating layer, a free magnetic layer, and a second electrode. When a voltage is applied across the magnetic OTP memory cell, the resistance of the MTJ stack and the gating transistor form a voltage divider to apply a large voltage across the MTJ stack to breakdown the tunnel barrier to short the fixed layer to the free layer. The integrated circuit has multiple MRAM arrays configured such that each of the multiple MRAM arrays have performance and density criteria that match MOS transistor based memory including SRAM, DRAM, and flash memory. The integrated circuit may include a functional logic unit connected with the magnetic OTP memory arrays and the MRAM arrays for providing digital data storage.

Abstract translation: 集成电路包括由具有固定磁性层的MTJ堆叠的多个磁性OTP存储单元形成的磁性OTP存储器阵列，隧道势垒绝缘层，自由磁性层和第二电极。 当跨越磁性OTP存储单元施加电压时，MTJ堆叠和门控晶体管的电阻形成分压器，以跨越MTJ堆叠施加大电压以击穿隧道势垒以将固定层短路到自由层。 集成电路具有多个MRAM阵列，其配置成使得多个MRAM阵列中的每一个具有与包括SRAM，DRAM和闪速存储器在内的基于MOS晶体管的存储器的性能和密度标准。 集成电路可以包括与磁性OTP存储器阵列连接的功能逻辑单元和用于提供数字数据存储的MRAM阵列。

公开(公告)号：WO2014043465A1

公开(公告)日：2014-03-20

申请号：PCT/US2013/059655

申请日：2013-09-13

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： SONG, Suping ,  GUAN, Lijie ,  MIN, Tai ,  TANG, Yuhui

IPC: G11B5/127 ,  G11B5/31

CPC classification number: G11B5/315 ,  G11B5/1278 ,  G11B5/3116 ,  G11B5/3163

Abstract: A magnetic recording head is fabricated with a pole tip shielded laterally on its sides by a pair of symmetrically disposed side shields formed of porous heterogeneous material that contains non-magnetic inclusions. The non-magnetic inclusions, when properly incorporated within the magnetic matrix of the shields, promote the formation of flux loops within the shields that have portions that are parallel to the ABS and do not display locally disorganized and dynamic regions of flux during the creation of magnetic transitions within the recording medium by the magnetic pole. These flux loop portions, combine with the magnetic flux emerging from the main pole to create a net writing field that significantly reduces adjacent track erasures (ATE) and wide area erasures (WATE).

Abstract translation: 制造磁记录头，其极侧通过由包含非磁性夹杂物的多孔异质材料形成的一对对称设置的侧屏蔽侧向屏蔽。 当非磁性夹杂物适当地并入屏蔽体的磁矩阵中时，促进在屏蔽体内形成具有与ABS平行的部分的磁通环，并且在创建过程中不显示局部无组织和动态的磁通区域 通过磁极在记录介质内的磁转变。 这些磁通回路部分与从主极产生的磁通相结合，形成一个净写入场，显着减少了相邻轨道擦除（ATE）和广域擦除（WATE）。

公开(公告)号：WO2014036101A1

公开(公告)日：2014-03-06

申请号：PCT/US2013/057018

申请日：2013-08-28

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： HUANG, Kenlin ,  CHIN, Yuan-Tung ,  ZHONG, Tom ,  TORNG, Chyu-Jiuh

IPC: H01F10/32 ,  H01F41/30 ,  H01F41/32 ,  G01R33/09 ,  G11C11/16 ,  H01L43/12

CPC classification number: G01R33/098 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/308 ,  H01F41/325 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic thin film deposition is patterned and protected from oxidation during subsequent processes, such as bit line formation, by an oxidation-prevention encapsulation layer of SiN. The SiN layer is then itself protected during the processing by a metal overlayer, preferably of Ta, Al, TiN, TaN or W. A sequence of low pressure plasma etches, using Oxygen, Cl 2 , BCl 3 and C 2 H 4 chemistries provide selectivity of the metal overlayer to various oxide layers and to the photo- resist hard masks used in patterning and metal layer and thereby allow the formation of bit lines while maintaining the integrity of the SiN layer.

Abstract translation: 通过SiN的防氧化封装层，在随后的工艺（例如位线形成）中图案化和保护磁性薄膜沉积物免于氧化。 然后，SiN层在金属覆盖层，优选Ta，Al，TiN，TaN或W的处理过程中自身受到保护。使用氧气，Cl2，BCl3和C2H4化学物质的低压等离子体蚀刻序列提供金属覆层的选择性 到各种氧化物层和用于图案化和金属层中的光致抗蚀剂硬掩模，从而允许形成位线，同时保持SiN层的完整性。

公开(公告)号：WO2013151837A1

公开(公告)日：2013-10-10

申请号：PCT/US2013/034003

申请日：2013-03-27

Applicant: HEADWAY TECHNOLOGIES, INC ,  JAN, Guenole ,  TONG, Ru-Ying

Inventor： JAN, Guenole ,  TONG, Ru-Ying

IPC: G11B5/39

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/308 ,  H01L43/08

Abstract: A ferromagnetic layer is capped with a metallic oxide (or nitride) layer that provides a perpendicular-to-plane magnetic anisotropy to the layer. The surface of the ferromagnetic layer is treated with a plasma to prevent diffusion of oxygen (or nitrogen) into the layer interior. An exemplary metallic oxide layer is formed as a layer of metallic Mg that is plasma treated to reduce its grain size and enhance the diffusivity of oxygen into its interior. Then the plasma treated Mg layer is naturally oxidized and, optionally, is again plasma treated to reduce its thickness and remove the oxygen rich upper surface.

Abstract translation: 铁磁层被覆有金属氧化物（或氮化物）层，其向层提供垂直于平面的磁各向异性。 用等离子体处理铁磁层的表面以防止氧（或氮）扩散到层内部。 金属氧化物层形成为金属Mg层，其被等离子体处理以降低其晶粒尺寸并增加氧气进入其内部的扩散性。 然后等离子体处理的Mg层被天然氧化，并且任选地再次进行等离子体处理以减小其厚度并去除富氧上表面。

公开(公告)号：WO2013130195A1

公开(公告)日：2013-09-06

申请号：PCT/US2013/022877

申请日：2013-01-24

Applicant: HEADWAY TECHNOLOGIES, INC. ,  WANG, Yu-jen ,  KULA, Witold ,  TONG, Ru, Ying ,  JAN, Guenole

Inventor： WANG, Yu-jen ,  KULA, Witold ,  TONG, Ru, Ying ,  JAN, Guenole

IPC: H01L29/82

CPC classification number: H01L43/12 ,  G01R33/093 ,  G11B5/3906 ,  G11B5/3909 ,  G11B5/3929 ,  G11B5/66 ,  G11B5/84 ,  G11C11/15 ,  G11C11/161 ,  H01F10/123 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/3295 ,  H01F41/305 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H03B15/006 ,  Y10T428/1107 ,  Y10T428/1121 ,  Y10T428/1143

Abstract: Enhanced He and Hk in addition to higher thermal stability up to at least 400°C are achieved in magnetic devices by adding dusting layers on top and bottom surfaces of a spacer in a synthetic antiferromagnetic (SAF) structure to give a RL1/DL1/spacer/DL2/RL2 reference layer configuration where RL1 and RL2 layers exhibit perpendicular magnetic anisotropy (PMA), the spacer induces antiferromagnetic coupling between RL1 and RL2, and DL1 and DL2 are dusting layers that enhance PMA. Dusting layers are deposited at room temperature to 400°C. RL1 and RL2 layers are selected from laminates such as (Ni/Co)n, L1o alloys, or rare earth-transition metal alloys. The reference layer may be incorporated in STT-MRAM memory elements or in spintronic devices including a spin transfer oscillator. Dusting layers and a similar SAF design may be employed in a free layer for Ku enhancement and to increase the retention time of a memory cell for STT-MRAM designs.

Abstract translation: 通过在合成反铁磁（SAF）结构中在间隔物的顶表面和底表面上添加除尘层，得到RL1 / DL1 /间隔物，通过在磁性器件中获得增强的He和Hk以及至多400℃的更高的热稳定性。 / DL2 / RL2参考层配置，其中RL1和RL2层呈现垂直磁各向异性（PMA），间隔物引起RL1和RL2之间的反铁磁耦合，DL1和DL2是增强PMA的除尘层。 除尘层在室温至400℃下沉积。 RL1和RL2层选自诸如（Ni / Co）n，L1o合金或稀土 - 过渡金属合金的层压体。 参考层可以并入STT-MRAM存储元件或包括自旋转移振荡器的自旋电子器件中。 可以在用于Ku增强的自由层中使用除尘层和类似的SAF设计，并且增加用于STT-MRAM设计的存储器单元的保留时间。