公开(公告)号：WO2015094549A3

公开(公告)日：2015-10-22

申请号：PCT/US2014066310

申请日：2014-11-19

Applicant: ASM IP HOLDING BV ,  ASM INC

Inventor： HAUKKA SUVI P ,  TANG FU ,  GIVENS MICHAEL E ,  MAES JAN WILLEM ,  XIE QI

IPC: H01L21/203

CPC classification number: H01L21/02568 ,  C23C16/0227 ,  C23C16/305 ,  C23C16/45525 ,  H01L21/02557 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/28264

Abstract: In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.

Abstract translation: 在一些方面中，提供了形成金属硫化物薄膜的方法。 根据一些方法，金属硫化物薄膜以循环方法沉积在反应空间中的基底上，其中至少一个循环包括交替地且顺序地使基底与第一气相金属反应物和第二气相硫 反应物。 在一些方面中，提供了在衬底表面上形成三维结构的方法。 在一些实施例中，该方法包括在基板表面上形成金属硫化物薄膜并在金属硫化物薄膜上形成覆盖层。 衬底表面可以包括高迁移率沟道。

公开(公告)号：WO2011049816A3

公开(公告)日：2011-10-13

申请号：PCT/US2010052741

申请日：2010-10-14

Applicant: ASM INT ,  ASM INC ,  BLOMBERG TOM E ,  TOIS EVA E ,  HUGGARE ROBERT ,  MAES JAN WILLEM ,  MACHKAOUTSAN VLADIMIR ,  PIERREUX DIETER

Inventor： BLOMBERG TOM E ,  TOIS EVA E ,  HUGGARE ROBERT ,  MAES JAN WILLEM ,  MACHKAOUTSAN VLADIMIR ,  PIERREUX DIETER

IPC: C23C14/06 ,  C23C14/02 ,  C23C14/20 ,  C23C16/02 ,  C23C16/30 ,  C23C16/44

CPC classification number: C23C16/34 ,  C23C16/36 ,  C23C16/409 ,  C23C16/45531

Abstract: Methods are disclosed herein for depositing a passivation layer comprising fluorine over a dielectric material that is sensitive to chlorine, bromine, and iodine. The passivation layer can protect the sensitive dielectric layer thereby enabling deposition using precursors comprising chlorine, bromine, and iodine over the passivation layer.

Abstract translation: 本文公开了用于在对氯，溴和碘敏感的介电材料上沉积包含氟的钝化层的方法。 钝化层可以保护敏感介电层，从而能够使用包含氯，溴和碘的前体在钝化层上进行沉积。

公开(公告)号：WO2010129431A3

公开(公告)日：2011-03-31

申请号：PCT/US2010033252

申请日：2010-04-30

Applicant: ASM INC ,  CONNER RAND ,  AGGARWAL RAVINDER K

Inventor： CONNER RAND ,  AGGARWAL RAVINDER K

IPC: H01L21/683 ,  C23C16/00 ,  G01K1/08 ,  G01K7/02 ,  H01L21/304

CPC classification number: H01L21/67248 ,  C23C16/4586 ,  G01K1/14 ,  G01K7/02

Abstract: A thermocouple having at least one inner alignment feature or at least one outer alignment feature, or a combination thereof for positively positioning and aligning at least one thermocouple junction within a bore formed in a susceptor ring of a semiconductor substrate processing reactor. The outer alignment feature is configured to positively align the junction(s) longitudinally within the bore. The inner alignment feature configured to positively position the junction(s) rotationally within the sheath of the thermocouple relative to the bore.

Abstract translation: 具有至少一个内部对准特征或至少一个外部对准特征或其组合的热电偶用于在半导体衬底处理反应器的基座环内形成的孔内积极地定位和对准至少一个热电偶结。 外部对准特征构造成在孔内纵向对准接头。 所述内部对准特征构造成相对于所述孔将所述接合部在所述热电偶的护套内旋转地定位。

公开(公告)号：WO2010126675A3

公开(公告)日：2011-01-13

申请号：PCT/US2010029562

申请日：2010-04-01

Applicant: ASM INC

Inventor： RAGHAVAN SRINI ,  SHERO ERIC ,  VERGHESE MOHITH

IPC: H01L21/02

CPC classification number: C09K13/02 ,  C11D7/06 ,  C11D7/10 ,  C11D7/265 ,  C11D11/0041 ,  C23C16/4405 ,  C23C16/4407 ,  C23C16/45525 ,  C23G1/18 ,  C23G1/205 ,  C23G1/22

Abstract: Compositions, methods, and systems permit selectively etching metal oxide from reactor metal parts (e.g., titanium and/or titanium alloys). The etching composition comprises an alkali metal hydroxide and gallic acid. The method is useful for cleaning reaction chambers used in the deposition of metal oxide films such as aluminum oxide.

Abstract translation: 组合物，方法和系统允许从反应器金属部件（例如钛和/或钛合金）中选择性地蚀刻金属氧化物。 蚀刻组合物包含碱金属氢氧化物和没食子酸。 该方法对于用于沉积金属氧化物膜如氧化铝的反应室是有用的。

公开(公告)号：WO2009132207A2

公开(公告)日：2009-10-29

申请号：PCT/US2009041561

申请日：2009-04-23

Applicant: ASM INT ,  ASM INC

Inventor： PORE VILJAMI ,  HATANPAEAE TIMO ,  RITALA MIKKO ,  LESKELA MARKKU

IPC: C23C16/44 ,  C23C16/06 ,  C23C16/16 ,  H01L21/205

CPC classification number: C07F11/005 ,  C23C16/306 ,  C23C16/45553 ,  H01L21/0256 ,  H01L21/02562 ,  H01L21/0262 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1616 ,  Y02P20/582

Abstract: Atomic layer deposition (ALD) processes for forming Te-containing thin films, such as Sb-Te, Ge-Te, Ge-Sb-Te, Bi-Te, and Zn-Te thin films are provided. ALD processes are also provided for forming Se-containing thin films, such as Sb-Se, Ge-Se, Ge-Sb-Se, Bi-Se, and Zn-Se thin films are also provided. Te and Se precursors of the formula (Te,Se)( SiR1R2R3)2 are preferably used, wherein R1, R2, and R3 are alkyl groups. Methods are also provided for synthesizing these Te and Se precursors. Methods are also provided for using the Te and Se thin films in phase change memory devices.

Abstract translation: 提供了用于形成诸如Sb-Te，Ge-Te，Ge-Sb-Te，Bi-Te和Zn-Te薄膜的Te含量薄膜的原子层沉积（ALD）工艺。 还提供了用于形成含Se的薄膜的ALD工艺，例如Sb-Se，Ge-Se，Ge-Sb-Se，Bi-Se和Zn-Se薄膜。 优选使用式（Te，Se）（SiR 1 R 2 R 3）2的Te和Se前体，其中R 1，R 2和R 3是烷基。 还提供了用于合成这些Te和Se前体的方法。 还提供了在相变存储器件中使用Te和Se薄膜的方法。

公开(公告)号：WO2008070302A3

公开(公告)日：2008-12-31

申请号：PCT/US2007081970

申请日：2007-10-19

Applicant: ASM INC

Inventor： HARVEY ELLIS G

IPC: B25J15/06

CPC classification number: H01L21/6838

Abstract: A Bernoulli wand (50) for transporting semiconductor wafers. The wand (50) has a head portion (54) having a plurality of gas outlets (74, 75) configured to produce a flow of gas along an upper surface of a wafer to create a pressure differential between the upper surface of the wafer and the lower surface of the wafer. The pressure differential generates a lift force that supports the wafer below the head portion (54) of the wand in a substantially non-contacting manner, employing the Bernoulli principle. The wand (50) has independently controllable gas channels (70, 80) configured to provide flow to different sets of gas outlet holes (74, 75). The gas outlet holes (74, 75) and gas channels (70, 80) are configured to support a wafer using the Bernoulli principle.

Abstract translation: 用于运输半导体晶圆的伯努利棒（50）。 所述棒（50）具有头部（54），所述头部具有多个气体出口（74,75），所述多个气体出口构造成沿着晶片的上表面产生气流，以在所述晶片的上表面和 晶片的下表面。 压力差产生提升力，其以基本上非接触的方式使用伯努利原理支撑晶片的头部（54）下方的晶片。 所述棒（50）具有可独立控制的气体通道（70,80），其构造成向不同组的气体出口孔（74,75）提供流量。 气体出口孔（74,75）和气体通道（70,80）构造成使用伯努利原理来支撑晶片。

公开(公告)号：WO2005116304A3

公开(公告)日：2007-01-25

申请号：PCT/US2005013674

申请日：2005-04-21

Applicant: ASM INC

Inventor： BAUER MATTHIAS

IPC: H01L21/20 ,  C30B1/00 ,  C30B25/02 ,  C30B25/16 ,  C30B29/52 ,  H01L21/205 ,  H01L21/285 ,  H01L21/31 ,  H01L21/36 ,  H01L21/469

CPC classification number: C30B25/02 ,  C30B25/16 ,  C30B29/52 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28525 ,  H01L21/28562

Abstract: A method for depositing an in situ doped epitaxial semiconductor layer comprises maintaining a pressure of greater than about 80 torr in a process chamber housing a patterned substrate. The method further comprises providing a flow of dichlorosilane to the process chamber. The method further comprises providing a flow of a dopant hydride to the process chamber. The method further comprises selectively depositing the epitaxial semiconductor layer on single crystal material on the patterned substrate at a rate of greater than about 3 nm min -1 .

Abstract translation: 用于沉积原位掺杂的外延半导体层的方法包括在容纳图案化衬底的处理室中保持大于约80托的压力。 该方法还包括向处理室提供二氯硅烷流。 该方法还包括向处理室提供掺杂剂氢化物的流。 该方法还包括以大于约3nm min -1的速率在图案化衬底上的单晶材料上选择性地沉积外延半导体层。

公开(公告)号：WO2006083909A3

公开(公告)日：2006-10-19

申请号：PCT/US2006003465

申请日：2006-01-31

Applicant: ASM INC ,  BAUER MATTHIAS ,  WEEKS KEITH DORAN ,  TOMASINI PIERRE ,  CODY NYLES

Inventor： BAUER MATTHIAS ,  WEEKS KEITH DORAN ,  TOMASINI PIERRE ,  CODY NYLES

IPC: C30B29/06 ,  C23C16/24 ,  C30B25/02 ,  H01L21/205 ,  H01L29/10

CPC classification number: H01L29/7848 ,  C23C16/04 ,  C23C16/22 ,  C23C16/24 ,  C23C16/32 ,  C23C16/325 ,  C23C16/45512 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/32056 ,  H01L21/3215 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: Methods of making Si-containing films that contain relatively high levels of substitutional dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain 2.4 atomic % or greater substitutional carbon. Substitutionally doped Si-containing films may be selectively deposited onto the crystalline surfaces of mixed substrates by introducing an etchant gas during deposition.

Abstract translation: 含有相对高含量的取代掺杂剂的含Si膜的方法涉及使用丙硅烷和掺杂剂前体的化学气相沉积。 可以获得非常高的替代掺入水平，包括含有2.4原子％或更大的取代碳的晶体硅膜。 通过在沉积期间引入蚀刻剂气体，可将选择性地掺杂的含Si薄膜选择性地沉积到混合基板的晶体表面上。

公开(公告)号：WO2005042160A3

公开(公告)日：2006-02-02

申请号：PCT/US2004036301

申请日：2004-10-29

Applicant: ASM INC ,  SHERO ERIC J ,  MOHITH VERGHESE E

Inventor： SHERO ERIC J ,  MOHITH VERGHESE E

IPC: C23C16/44 ,  C23C16/455 ,  C25F1/00 ,  F26B3/00 ,  H01L21/00

CPC classification number: C23C16/4412 ,  C23C16/45548 ,  C23C16/45591 ,  H01L21/67017

Abstract: A reactor defines a reaction chamber for processing a substrate. The reactor comprises a first inlet for providing a first reactant and to the reaction chamber and a second inlet for a second reactant to the reaction chamber. A first exhaust outlet removes gases from the reaction chamber. A second exhaust outlet removes gases from the reaction chamber. A flow control system is configured to alternately constrict flow through the first and second exhaust outlets. The reactor chamber is configured to for a diffusion barrier within the reaction chamber.

Abstract translation: 反应器限定用于处理基板的反应室。 反应器包括用于提供第一反应物和反应室的第一入口和用于反应室的第二反应物的第二入口。 第一排气口从反应室中除去气体。 第二排气口从反应室中除去气体。 流量控制系统被配置为交替地收缩通过第一和第二排气出口的流动。 反应室被配置成在反应室内用于扩散阻挡层。

公开(公告)号：WO2004081987A2

公开(公告)日：2004-09-23

申请号：PCT/US2004007386

申请日：2004-03-11

Applicant: ASM INC ,  ARENA CHANTAL ,  TOMASINI PIERRE ,  CODY NYLES

Inventor： ARENA CHANTAL ,  TOMASINI PIERRE ,  CODY NYLES

IPC: C30B25/02 ,  C30B29/52 ,  H01L21/20 ,  H01L21/322 ,  H01L29/10 ,  H01L

CPC classification number: H01L21/322 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02656 ,  H01L29/1054

Abstract: A method for forming strain-relaxed SiGe films comprises depositing a graded strained SiGe layer on a substrate in which the concentration of Ge is greater at the interface with the substrate than at the top of the layer (Figure 1). The strained SiGe film is subsequently oxidized, producing a strain-relaxed SiGe film with a substantially uniform Ge concentration across the thickness of the film. The relaxed SiGe layer may be used to form a strained silicon layer on a substrate.

Abstract translation: 用于形成应变松弛SiGe膜的方法包括在衬底上沉积梯度应变SiGe层，其中Ge的浓度在与衬底的界面处比在层的顶部大（图1）。 应变的SiGe膜随后被氧化，产生在膜的厚度上具有基本上均匀的Ge浓度的应变松弛的SiGe膜。 可以使用松弛的SiGe层在衬底上形成应变硅层。