公开(公告)号：WO2010117964A2

公开(公告)日：2010-10-14

申请号：PCT/US2010/030008

申请日：2010-04-05

Applicant: LAM RESEARCH CORPORATION ,  JI, Bing ,  TAKESHITA, Kenji ,  BAILEY, Andrew D., III ,  HUDSON, Eric A. ,  MORAVEJ, Maryam ,  SIRARD, Stephen M. ,  KO, Jungmin ,  LE, Daniel ,  HEFTY, Robert C. ,  CHENG, Yu ,  DELGADINO, Gerardo A. ,  YEN, Bi-Ming

Inventor： JI, Bing ,  TAKESHITA, Kenji ,  BAILEY, Andrew D., III ,  HUDSON, Eric A. ,  MORAVEJ, Maryam ,  SIRARD, Stephen M. ,  KO, Jungmin ,  LE, Daniel ,  HEFTY, Robert C. ,  CHENG, Yu ,  DELGADINO, Gerardo A. ,  YEN, Bi-Ming

IPC: H01L21/3065 ,  H05H1/34

CPC classification number: H01L21/31116 ,  H01L21/02063 ,  H01L21/31138

Abstract: A method for etching features in a low-k dielectric layer disposed below an organic mask is provided by an embodiment of the invention. Features are etched into the low-k dielectric layer through the organic mask. A fluorocarbon layer is deposited on the low-k dielectric layer. The fluorocarbon layer is cured. The organic mask is stripped.

Abstract translation: 通过本发明的实施例提供了一种用于蚀刻位于有机掩模下方的低k电介质层中的特征的方法。 通过有机掩模将特征蚀刻到低k电介质层中。 在低k电介质层上沉积氟碳层。 氟碳层被固化。 剥去有机面膜。

公开(公告)号：WO2009046032A1

公开(公告)日：2009-04-09

申请号：PCT/US2008/078338

申请日：2008-09-30

Applicant: LAM RESEARCH CORPORATION ,  CHEN, Jack ,  BAILEY, Andrew, D., III ,  SHAREEF, Iqbal

Inventor： CHEN, Jack ,  BAILEY, Andrew, D., III ,  SHAREEF, Iqbal

IPC: H01L21/3065

CPC classification number: H01L21/02087 ,  C23C16/455 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/67051 ,  H01L21/67069 ,  H01L21/6708

Abstract: A method for etching a bevel edge of a substrate in a processing chamber is provided. The method includes flowing an inert gas into a center region of the processing chamber defined above a center region of the substrate and flowing a mixture of an inert gas and a processing gas over an edge region of the substrate. The method farther includes striking a plasma in the edge region, wherein the flow of the inert gas and the flow of the mixture maintain a mass fraction of the processing gas substantially constant. A processing chamber configured to clean a bevel edge of a substrate is also provided.

Abstract translation: 提供了一种用于在处理室中蚀刻衬底的斜边缘的方法。 该方法包括将惰性气体流入位于衬底的中心区域上方的处理室的中心区域，并使惰性气体和处理气体的混合物流过衬底的边缘区域。 该方法进一步包括在边缘区域中冲击等离子体，其中惰性气体的流动和混合物的流动保持处理气体的质量分数基本上恒定。 还提供了一种构造成清洁基板的斜边缘的处理室。

公开(公告)号：WO2007130630A3

公开(公告)日：2008-12-31

申请号：PCT/US2007010929

申请日：2007-05-04

Applicant: LAM RES CORP ,  YOON HYUNGSUK ALEXANDER ,  BAILEY ANDREW D III ,  JASON A RYDER ,  WILCOXSON MARK H ,  GASPARITSCH JEFFREY G ,  RANDY JOHNSON ,  HOFFMANN STEPHAN P

Inventor： YOON HYUNGSUK ALEXANDER ,  BAILEY ANDREW D III ,  JASON A RYDER ,  WILCOXSON MARK H ,  GASPARITSCH JEFFREY G ,  RANDY JOHNSON ,  HOFFMANN STEPHAN P

IPC: B08B11/02

CPC classification number: H01L21/67046 ,  Y10S134/902

Abstract: An apparatus, system and method for cleaning a substrate edge include a bristle brush unit that cleans bevel polymers deposited on substrate edges using frictional contact in the presence of cleaning chemistry. The bristle brush unit is made up of a plurality of outwardly extending vanes and is mounted on a rotating shaft. An abrasive material is distributed throughout and within the outwardly extending vanes of the bristle brush unit to provide the frictional contact. The bristle brush unit cleans the edge of the substrate by allowing frictional contact of the plurality of abrasive particles with the edge of the substrate in the presence of fluids, such as cleaning chemistry, to cut, rip and tear the bevel polymer from the edge of the substrate.

Abstract translation: 用于清洁基材边缘的装置，系统和方法包括刷毛刷单元，其在清洁化学品存在下使用摩擦接触来清洁沉积在基板边缘上的斜面聚合物。 刷毛单元由多个向外延伸的叶片组成，并安装在旋转轴上。 研磨材料分布在刷毛刷单元的向外延伸的叶片内部和内部，以提供摩擦接触。 刷毛刷单元通过在诸如清洁化学的流体存在下允许多个磨料颗粒与基材的边缘摩擦接触来清洁基材的边缘，以从斜面聚合物的边缘切割，撕裂和撕裂斜面聚合物 底物。

公开(公告)号：WO2008091668A1

公开(公告)日：2008-07-31

申请号：PCT/US2008/000940

申请日：2008-01-24

Applicant: LAM RESEARCH CORPORATION ,  BAILEY, Andrew, D., III ,  SCHOEPP, Alan M. ,  SEXTON, Gregory ,  KUTHI, Andras ,  KIM, Yunsang ,  KENNEDY, William S.

Inventor： BAILEY, Andrew, D., III ,  SCHOEPP, Alan M. ,  SEXTON, Gregory ,  KUTHI, Andras ,  KIM, Yunsang ,  KENNEDY, William S.

IPC: H01L21/3065

CPC classification number: H01L21/0209 ,  H01J37/32366 ,  H01J37/32568 ,  H01J2237/335 ,  H01L21/67069

Abstract: A device for cleaning a bevel edge of a semiconductor substrate. The device includes a lower electrode assembly that has a top surface and is adapted to support the substrate and an upper electrode assembly that has a bottom surface opposing the top surface. The lower and upper electrode assemblies generate plasma for cleaning the bevel edge of the substrate disposed between the top and bottom surfaces during operation. The device also includes a mechanism for suspending the upper electrode assembly over the lower support and adjusting the tilt angle and horizontal translation of the bottom surface relative to the top surface.

Abstract translation: 一种用于清洁半导体衬底的斜边缘的装置。 该装置包括具有顶表面并适于支撑基底的下电极组件和具有与顶表面相对的底表面的上电极组件。 下部和上部电极组件在操作期间产生用于清洁设置在顶部和底部表面之间的衬底的斜面边缘的等离子体。 该装置还包括用于将上电极组件悬挂在下支撑件上并且调节底表面相对于顶表面的倾斜角度和水平平移的机构。

公开(公告)号：WO2007038580A3

公开(公告)日：2007-08-09

申请号：PCT/US2006037648

申请日：2006-09-26

Applicant: LAM RES CORP ,  KIM YUNSANG ,  BAILEY ANDREW D III

Inventor： KIM YUNSANG ,  BAILEY ANDREW D III

IPC: H01J37/32

CPC classification number: H01J37/32532 ,  H01J37/32357 ,  H01J37/3244 ,  H01J37/32862

Abstract: Improved mechanisms of removal of etch byproducts, dielectric films and metal films near the substrate bevel edge, and etch byproducts on substrate backside and chamber interior is provided to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. An exemplary plasma etch processing chamber configured to clean a bevel edge of a substrate is provided. The chamber includes a bottom edge electrode surrounding a substrate support in the plasma processing chamber, wherein the substrate support is configured to receive the substrate and the bottom edge electrode and the substrate support are electrically isolated from each other by a bottom dielectric ring. The chamber also includes a top edge electrode surrounding a gas distribution plate opposing the substrate support, wherein the top edge electrode and the gas distribution plate are electrically isolated from each other by a top dielectric ring, and the top edge electrode and the bottom edge electrode are configured to generate a cleaning plasma to clean the bevel edge of the substrate.

Abstract translation: 提供了去除蚀刻副产物，电介质膜和金属薄膜附近基板斜边缘的改进机理，以及衬底背面和腔室内部的蚀刻副产物，以避免聚合物副产物和沉积膜的堆积并提高工艺产率。 提供了一种构造成清洁衬底的斜边缘的示例性等离子体蚀刻处理室。 所述腔室包括围绕所述等离子体处理室中的衬底支撑件的底部边缘电极，其中所述衬底支撑件构造成接收所述衬底，并且所述底部边缘电极和所述衬底支撑件通过底部电介质环彼此电隔离。 该室还包括围绕与衬底支撑件相对的气体分配板的顶部边缘电极，其中顶部边缘电极和气体分布板通过顶部介电环彼此电隔离，并且顶部边缘电极和底部边缘电极 被配置为产生清洁等离子体以清洁基板的斜边缘。

公开(公告)号：WO2007005211A3

公开(公告)日：2007-05-03

申请号：PCT/US2006023033

申请日：2006-06-13

Applicant: LAM RES CORP ,  BAILEY ANDREW D III

Inventor： BAILEY ANDREW D III

IPC: G01R35/00

CPC classification number: G01B7/105 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of determining a first thickness of a first conductive film formed of a first conductive material on a target substrate is disclosed. The method includes positioning a first eddy current sensor near a set of positions on the target substrate. The method also includes measuring, using the first eddy current sensor, a first set of electrical responses that includes at least one of a first voltage measurement and a first current measurement. The method further includes correcting the set of first electrical responses using a temperature-dependent compensation factor, thereby obtaining a corrected first set of electrical responses, the temperature-dependent compensation factor being obtained from a calibration substrate different from the target substrate, the calibration substrate having a second conductive film formed of a second conductive material that is substantially similar to the first conductive material of the target substrate; and determining the first thickness using the corrected first set of electrical responses.

Abstract translation: 公开了确定在目标基板上由第一导电材料形成的第一导电膜的第一厚度的方法。 该方法包括将第一涡流传感器定位在目标基板上的一组位置附近。 该方法还包括使用第一涡流传感器测量包括第一电压测量值和第一电流测量值中的至少一个的第一组电响应。 该方法还包括使用取决于温度的补偿因子来校正该组第一电响应，从而获得校正的第一组电响应，取决于温度的补偿因子是从与目标基板不同的校准基板获得的，校准基板 具有由与目标衬底的第一导电材料基本相似的第二导电材料形成的第二导电膜; 以及使用经校正的第一组电响应来确定第一厚度。

公开(公告)号：WO2004084266A2

公开(公告)日：2004-09-30

申请号：PCT/US2004/007527

申请日：2004-03-10

Applicant: LAM RESEARCH CORPORATION ,  LOHOKARE, Shrikant, P. ,  BAILEY, Andrew, D., III ,  HEMKER, David ,  COOK, Joel, M.

Inventor： LOHOKARE, Shrikant, P. ,  BAILEY, Andrew, D., III ,  HEMKER, David ,  COOK, Joel, M.

IPC: H01L

CPC classification number: H01L21/7684 ,  H01L21/31116 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/32136

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

Abstract translation: 用于平坦化图案化半导体衬底的系统和方法包括接收图案化的半导体衬底。 图案化半导体衬底具有填充图案中的多个特征的导电互连材料。 导电互连材料具有覆盖层部分。 覆盖层部分具有局部不均匀性。 去除覆盖层部分的大部分以平坦化上覆层部分。 映射基本上局部平坦化的覆盖层部分以确定全局不均匀性。 基本上局部平坦化的覆盖层部分被蚀刻以基本上去除全局不均匀性。

公开(公告)号：WO2004030082A1

公开(公告)日：2004-04-08

申请号：PCT/US2003/030391

申请日：2003-09-26

Applicant: LAM RESEARCH CORPORATION ,  YADAV, Puneet ,  BAILEY, Andrew, D., III

Inventor： YADAV, Puneet ,  BAILEY, Andrew, D., III

IPC: H01L21/66

CPC classification number: H01L22/20

Abstract: A method for adjusting a data set defining a set of process runs, each process run having a set of data corresponding to a set of variables for a wafer processing operation is provided. A model derived from a data set is received (116). A new data set corresponding to one process run is received (118). The new data set is projected to the model (120). An outlier data point produced as a result of the projecting is identified (122). A variable corresponding to the one outlier data point is identified, the identified variable exhibiting a high contribution (126). A value for the variable from the new data set is identified. Whether the value for the variable is unimportant is determined (128). A normalized matrix of data is created, using random data and the variable that was determined to be unimportant from each of the new data set and the data set (132). The data set is updated with the normalized matrix of data.

Abstract translation: 提供一种用于调整定义一组处理运行的数据集的方法，每个处理运行具有与用于晶片处理操作的一组变量相对应的一组数据。 接收从数据集导出的模型（116）。 接收对应于一个进程运行的新数据集（118）。 新数据集投影到模型（120）。 识别作为投影的结果产生的异常值数据点（122）。 识别对应于一个异常数据点的变量，所识别的变量表现出高贡献（126）。 识别来自新数据集的变量的值。 确定变量的值是否不重要（128）。 使用随机数据和被确定为与每个新数据集和数据集不重要的变量（132）来创建数据的归一化矩阵。 数据集用数据的归一化矩阵更新。

公开(公告)号：WO2003096765A3

公开(公告)日：2003-11-20

申请号：PCT/US2003/013597

申请日：2003-05-01

Applicant: LAM RESEARCH CORPORATION ,  HOWALD, Arthur, M. ,  KUTHI, Andras ,  BAILEY, Andrew, D., III ,  BERNEY, Butch

Inventor： HOWALD, Arthur, M. ,  KUTHI, Andras ,  BAILEY, Andrew, D., III ,  BERNEY, Butch

IPC: H01J37/32

Abstract: A plasma processing chamber for processing a substrate to form electronic components thereon is disclosed. The plasma processing chamber includes a plasma-facing component (602) having a plasma-facing surface oriented toward plasma in the plasma processing chamber during processing of the substrate, the plasma-facing component being electrically isolated from a ground terminal. The plasma processing chamber further includes a grounding arrangement (600) coupled to the plasma-facing component, the grounding arrangement including a first resistance circuit (610) disposed in a first current path between the plasma-facing component and the ground terminal. The grounding arrangement further includes a RF filter arrangement (604, 610) disposed in at least one other current path between the plasma-facing component and the ground terminal, wherein a resistance value of the first resistance circuit is selected to substantially eliminate arcing between the plasma and the plasma-facing component during the processing of the substrate.

公开(公告)号：WO03096765A2

公开(公告)日：2003-11-20

申请号：PCT/US0313597

申请日：2003-05-01

Applicant: LAM RES CORP ,  HOWALD ARTHUR M ,  KUTHI ANDRAS ,  BAILEY ANDREW D III ,  BERNEY BUTCH

Inventor： HOWALD ARTHUR M ,  KUTHI ANDRAS ,  BAILEY ANDREW D III ,  BERNEY BUTCH

IPC: H05H1/46 ,  C23C16/00 ,  C23C16/50 ,  H01J37/32 ,  H01L21/205 ,  H01L21/306 ,  H01L21/3065 ,  H05H1/00

CPC classification number: H01J37/32477 ,  H01J37/32623

Abstract: A plasma processing chamber for processing a substrate to form electronic components thereon is disclosed. The plasma processing chamber includes a plasma-facing component having a plasma-facing surface oriented toward plasma in the plasma processing chamber during processing of the substrate, the plasma-facing component being electrically isolated from a ground terminal. The plasma processing chamber further includes a grounding arrangement coupled to the plasma-facing component, the grounding arrangement including a first resistance circuit disposed in a first current path between the plasma-facing component and the ground terminal. The grounding arrangement further includes a RF filter arrangement disposed in at least one other current path between the plasma-facing component and the ground terminal, wherein a resistance value of the first resistance circuit is selected to substantially eliminate arcing between the plasma and the plasma-facing component during the processing of the substrate.

Abstract translation: 公开了一种用于处理基板以在其上形成电子部件的等离子体处理室。 等离子体处理室包括在处理基板期间在等离子体处理室中具有朝向等离子体的等离子体面向表面的等离子体面向部件，等离子体面向部件与接地端子电隔离。 等离子体处理室还包括耦合到等离子体面向部件的接地装置，接地装置包括设置在等离子体面向部件和接地端子之间的第一电流路径中的第一电阻电路。 接地装置还包括设置在等离子体面向部件和接地端子之间的至少一个其它电流通路中的RF滤波器装置，其中选择第一电阻电路的电阻值以基本上消除等离子体和等离子体 - 在处理基板期间面对部件。