公开(公告)号：WO2008005377A3

公开(公告)日：2008-01-10

申请号：PCT/US2007/015224

申请日：2007-06-28

Applicant: INTEL CORPORATION ,  CURELLO, Giuseppe ,  POST, Ian, R. ,  JAN, Chia-hong ,  BOHR, Mark

Inventor： CURELLO, Giuseppe ,  POST, Ian, R. ,  JAN, Chia-hong ,  BOHR, Mark

IPC: H01L21/336 ,  H01L29/78

Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.

公开(公告)号：WO2005098962A1

公开(公告)日：2005-10-20

申请号：PCT/US2005/010159

申请日：2005-03-25

Applicant: INTEL CORPORATION ,  CURELLO, Giuseppe ,  HOFFMANN, Thomas ,  ARMSTRONG, Mark

Inventor： CURELLO, Giuseppe ,  HOFFMANN, Thomas ,  ARMSTRONG, Mark

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/7843 ,  Y10S438/938

Abstract: A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.

Abstract translation: 具有高拉伸应力的半导体器件。 半导体器件包括具有源极区和漏极区的衬底。 源极区域和漏极区域中的每一个分别包括多个分离的源极部分和漏极部分。 在源极区的两个分离的源极部分和漏极区域的两个分离的漏极部分之间形成浅沟槽隔离（STI）区域。 在基板上形成栅叠层。 在衬底上形成拉伸诱导层。 拉伸感应层覆盖STI区域，源极区域，漏极区域和栅极叠层。 拉伸诱导层是能够在基板中引起拉伸应力的绝缘体。

公开(公告)号：WO2007075305A1

公开(公告)日：2007-07-05

申请号：PCT/US2006/047034

申请日：2006-12-08

Applicant: INTEL CORPORATION ,  CURELLO, Giuseppe ,  MUDANAI, Sivakumar, P. ,  LINDERT, Nick ,  PIPES, Leonard, C. ,  SHAHEED, M., Reaz ,  TYAGI, Sunit

Inventor： CURELLO, Giuseppe ,  MUDANAI, Sivakumar, P. ,  LINDERT, Nick ,  PIPES, Leonard, C. ,  SHAHEED, M., Reaz ,  TYAGI, Sunit

IPC: H01L21/762

CPC classification number: H01L21/823481 ,  H01L21/823412

Abstract: A method including forming a transistor structure structure comprising a gate electrode over an active region of a substrate, the active region defined by a trench isolation structure and changing a performance of a narrow width transistor with respect to a wide width transistor by introducing a dopant into the active region adjacent an interface defined by the trench isolation structure and the gate electrode. A structure including a gate electrode formed on a substrate, an active region adjacent an interface defined by a trench isolation structure and a gate electrode and an implant within the active region to change a performance of a transistor.

Abstract translation: 一种包括在衬底的有源区上形成包括栅电极的晶体管结构结构的方法，所述有源区由沟槽隔离结构限定，并通过将掺杂剂引入到宽宽度晶体管中来改变窄宽晶体管的性能 邻接由沟槽隔离结构和栅电极限定的界面的有源区。 一种结构，包括形成在衬底上的栅电极，与由沟槽隔离结构限定的界面相邻的有源区和栅电极以及有源区内的注入以改变晶体管的性能。

公开(公告)号：WO2006039641A3

公开(公告)日：2006-04-13

申请号：PCT/US2005/035474

申请日：2005-09-29

Applicant: INTEL CORPORATION ,  HOFFMANN, Thomas ,  TYAGI, Sunit ,  CURELLO, Giuseppe ,  SELL, Bernhard ,  AUTH, Christopher

Inventor： HOFFMANN, Thomas ,  TYAGI, Sunit ,  CURELLO, Giuseppe ,  SELL, Bernhard ,  AUTH, Christopher

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/265

Abstract: A method of providing a halo implant region in a substrate of a MOS device having a gate electrode thereon and defining source/drain regions, a MOS device fabricated according to the above method, and a system comprising the MOS device. The method comprises: defining undercut recesses in the substrate at the source/drain regions thereof, the undercut recesses extending beneath the gate electrode; creating a halo implant region beneath the gate electrode between the recesses; and providing raised source/drain structures in the undercut recesses after creating the halo implant region.

公开(公告)号：WO2008005377A2

公开(公告)日：2008-01-10

申请号：PCT/US2007015224

申请日：2007-06-28

Applicant: INTEL CORP ,  CURELLO GIUSEPPE ,  POST IAN R ,  JAN CHIA-HONG ,  BOHR MARK

Inventor： CURELLO GIUSEPPE ,  POST IAN R ,  JAN CHIA-HONG ,  BOHR MARK

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.

Abstract translation: 在通过这种方法形成的第一类晶体管和器件上选择性地形成间隔物的方法。 该方法可以包括在其上具有不同类型的晶体管的衬底上沉积共形第一沉积层，在至少一类晶体管上沉积阻挡层，干蚀刻第一沉积层，去除阻挡层，沉积保形第二沉积 在所述衬底上干燥蚀刻所述第二沉积层并湿蚀刻剩余的第一沉积层。 与第二类晶体管的间隔物相比，器件可以包括具有较大间隔物的第一类晶体管。

公开(公告)号：WO2007102870A2

公开(公告)日：2007-09-13

申请号：PCT/US2006/047139

申请日：2006-12-06

Applicant: INTEL CORPORATION ,  CURELLO, Giuseppe ,  DESHPANDE, Hemant, V. ,  TYAGI, Sunit ,  BOHR, Mark

Inventor： CURELLO, Giuseppe ,  DESHPANDE, Hemant, V. ,  TYAGI, Sunit ,  BOHR, Mark

CPC classification number: H01L29/66628 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78687

Abstract: A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and suicide spike defects while preventing gate edge junction parasitic capacitance.

Abstract translation: MOS器件包括栅极堆叠，其包括设置在栅极电介质上的栅极电极，形成在栅极堆叠的横向相对侧上的第一间隔物和第二间隔物，靠近第一间隔物的源极区域，靠近第二间隔区的漏极区域 间隔物和位于栅叠层下方的沟道区，并设置在源区和漏区之间。 本发明的MOS器件还包括在沟道区域的下方并设置在源极区域和漏极区域之间的掩埋氧化物（BOX）区域。 BOX区域可以形成更深的源极和漏极区域，以减少晶体管电阻和硅化物尖峰缺陷，同时防止栅极边缘结的寄生电容。

公开(公告)号：WO2007102870A3

公开(公告)日：2007-12-06

申请号：PCT/US2006047139

申请日：2006-12-06

Applicant: INTEL CORP ,  CURELLO GIUSEPPE ,  DESHPANDE HEMANT V ,  TYAGI SUNIT ,  BOHR MARK

Inventor： CURELLO GIUSEPPE ,  DESHPANDE HEMANT V ,  TYAGI SUNIT ,  BOHR MARK

IPC: H01L21/336 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66628 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78687

Abstract: A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and suicide spike defects while preventing gate edge junction parasitic capacitance.

Abstract translation: MOS器件包括栅极叠层，该栅极叠层包括设置在栅极电介质上的栅极电极，形成在栅极叠层的横向相对侧上的第一间隔物和第二间隔物，靠近第一间隔物的源极区域，靠近第二间隔物的漏极区域 间隔体以及沟道区域，所述沟道区域位于栅极叠层的下方并且设置在源极区域和漏极区域之间。 本发明的MOS器件还包括埋置氧化物（BOX）区域，所述埋入氧化物（BOX）区域在沟道区域下方并且设置在源极区域和漏极区域之间。 BOX区域能够形成更深的源极和漏极区域，以减少晶体管电阻和硅化物尖峰缺陷，同时防止栅极边缘结寄生电容。

公开(公告)号：WO2009146008A1

公开(公告)日：2009-12-03

申请号：PCT/US2009/038710

申请日：2009-03-29

Applicant: INTEL CORPORATION ,  CURELLO, Giuseppe ,  POST, Ian, R. ,  LINDERT, Nick ,  HAFEZ, Walid, M. ,  JAN, Chia-Hong ,  BOHR, Mark, T.

Inventor： CURELLO, Giuseppe ,  POST, Ian, R. ,  LINDERT, Nick ,  HAFEZ, Walid, M. ,  JAN, Chia-Hong ,  BOHR, Mark, T.

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract translation: 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：WO2006039641A2

公开(公告)日：2006-04-13

申请号：PCT/US2005035474

申请日：2005-09-29

Applicant: INTEL CORP ,  HOFFMANN THOMAS ,  TYAGI SUNIT ,  CURELLO GIUSEPPE ,  SELL BERNHARD ,  AUTH CHRISTOPHER

Inventor： HOFFMANN THOMAS ,  TYAGI SUNIT ,  CURELLO GIUSEPPE ,  SELL BERNHARD ,  AUTH CHRISTOPHER

IPC: H01L21/336 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/41783 ,  H01L29/66492 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method of providing a halo implant region in a substrate of a MOS device having a gate electrode thereon and defining source/drain regions, a MOS device fabricated according to the above method, and a system comprising the MOS device. The method comprises: defining undercut recesses in the substrate at the source/drain regions thereof, the undercut recesses extending beneath the gate electrode; creating a halo implant region beneath the gate electrode between the recesses; and providing raised source/drain structures in the undercut recesses after creating the halo implant region.

Abstract translation: 一种在其上具有栅极并限定源极/漏极区的MOS器件的衬底中提供晕环注入区的方法，根据上述方法制造的MOS器件以及包括该MOS器件的系统。 该方法包括：在衬底的源/漏区处限定底切凹槽，底切凹槽在栅电极下方延伸; 在凹槽之间的栅电极下方形成晕环注入区; 以及在形成光晕注入区之后在底切凹槽中提供凸起的源极/漏极结构。