公开(公告)号：WO2019005156A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040493

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOYLE, Brian S. ,  KUO, Charles C. ,  DOCZY, Mark L. ,  SURI, Satyarth ,  ATANASOV, Sarah

Inventor： O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOYLE, Brian S. ,  KUO, Charles C. ,  DOCZY, Mark L. ,  SURI, Satyarth ,  ATANASOV, Sarah

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: A spin orbit torque (SOT) memory device includes a spin orbit torque electrode disposed in a dielectric layer above a substrate and a magnetic tunnel junction (MTJ) device disposed on a portion of the spin orbit torque electrode. The spin orbit torque electrode has an uppermost is 10-20 times larger than the MTJ device. The MTJ device includes a free layer disposed on the spin orbit torque electrode, a tunnel barrier such as an MgO disposed on the free layer and a fixed layer disposed on the tunnel barrier.

公开(公告)号：WO2017052637A1

公开(公告)日：2017-03-30

申请号：PCT/US2015/052436

申请日：2015-09-25

Applicant: INTEL CORPORATION ,  SURI, Satyarth ,  INDUKURI, Tejaswi, K. ,  OGUZ, Kaan ,  DOYLE, Brian, S. ,  O'BRIEN, Kevin, P. ,  DOCZY, Mark, L. ,  TURKOT, Robert, B., Jr.

Inventor： SURI, Satyarth ,  INDUKURI, Tejaswi, K. ,  OGUZ, Kaan ,  DOYLE, Brian, S. ,  O'BRIEN, Kevin, P. ,  DOCZY, Mark, L. ,  TURKOT, Robert, B., Jr.

IPC: H01L21/027

CPC classification number: H01L43/12

Abstract: Many silicon wafers include a mixture of structures including a first number of first structures, such as memory elements, having a first height and high component density and a second number of second structures, such as logic elements, having a second height that is greater than the first height and low component density. An etch process may be used to achieve the high component density using a multi-layer hardmask in which a first hardmask is formed on a surface of the semiconductor wafer. After forming the first hardmask, an etch process may be used to provide or otherwise facilitate the fabrication of a first number of first structures having a relatively high component density. A second hardmask may be selectively fabricated on at least a portion of the first hardmask. The combined thickness of first hardmask and the second hardmask may approximately equal the height of the second structures.

Abstract translation: 许多硅晶片包括包括第一数量的第一结构（诸如具有第一高度和高分量密度的存储元件）和第二数量的第二结构（诸如逻辑元件）的结构的混合物，其具有大于 第一高度和低分量密度。 可以使用蚀刻工艺来实现使用在半导体晶片的表面上形成第一硬掩模的多层硬掩模来实现高分量密度。 在形成第一硬掩模之后，可以使用蚀刻工艺来提供或以其它方式制造具有相对高的组分密度的第一数量的第一结构。 可以在第一硬掩模的至少一部分上选择性地制造第二硬掩模。 第一硬掩模和第二硬掩模的组合厚度可以近似等于第二结构的高度。

公开(公告)号：WO2014051724A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/045031

申请日：2013-06-10

Applicant: INTEL CORPORATION ,  KARPOV, Elijah V. ,  DOYLE, Brian S. ,  OGUZ, Kaan ,  SURI, Satyarth ,  CHAU, Robert S. ,  KUO, Charles C. ,  DOCZY, Mark L. ,  KENCKE, David L.

Inventor： KARPOV, Elijah V. ,  DOYLE, Brian S. ,  OGUZ, Kaan ,  SURI, Satyarth ,  CHAU, Robert S. ,  KUO, Charles C. ,  DOCZY, Mark L. ,  KENCKE, David L.

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  B82Y25/00 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  G11C11/5607 ,  H01F10/3254 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: Switching current in Spin- Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell.

Abstract translation: 旋转转矩存储器（STTM）中的切换电流可以减小。 磁存储单元用存储单元的写入线上的第一个脉冲驱动，以加热单元。 然后在写入线上用第二个脉冲驱动单元，以设置单元的状态。

公开(公告)号：WO2009088588A2

公开(公告)日：2009-07-16

申请号：PCT/US2008085249

申请日：2008-12-02

Applicant: INTEL CORP ,  METZ MATTHEW V ,  DOCZY MARK L ,  DEWEY GILBERT ,  KAVALIEROS JACK

Inventor： METZ MATTHEW V ,  DOCZY MARK L ,  DEWEY GILBERT ,  KAVALIEROS JACK

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/28088 ,  H01L21/324 ,  H01L29/105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/785

Abstract: Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate layer on the gate dielectric layer, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air.

Abstract translation: 描述形成微电子结构的方法。 那些方法可以包括在衬底上形成栅极电介质层，在栅极电介质层上形成金属栅极层，然后在原位在金属栅极层上形成多晶硅层，其中金属栅极层不暴露于空气中。

公开(公告)号：WO2019005158A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040497

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  OGUZ, Kaan ,  O'BRIEN, Kevin P. ,  DOYLE, Brian S. ,  KUO, Charles C. ,  DOCZY, Mark L.

Inventor： OGUZ, Kaan ,  O'BRIEN, Kevin P. ,  DOYLE, Brian S. ,  KUO, Charles C. ,  DOCZY, Mark L.

IPC: G11C11/16 ,  H01L43/08 ,  H01L27/22

Abstract: A spin orbit torque (SOT) memory device includes a spin orbit torque electrode disposed in a dielectric layer above a substrate and a magnetic tunnel junction (MTJ) device disposed on a portion of the spin orbit torque electrode. The spin orbit torque electrode has a uppermost surface area that is 10-20 times larger than a lowermost surface area of the MTJ memory device. The MTJ memory device includes a storage layer disposed on the spin orbit torque electrode, a tunnel barrier such as an MgO disposed on the storage layer and a fixed magnetic layer disposed on the tunnel barrier.

公开(公告)号：WO2019005157A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040496

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  WIEGAND, Christopher J. ,  RAHMAN, Tofizur ,  OUELLETTE, Daniel G. ,  SMITH, Angeline K. ,  BROCKMAN, Justin S. ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOCZY, Mark L. ,  DOYLE, Brian S. ,  GOLONZKA, Oleg ,  ALZATE VINASCO, Juan G.

Inventor： WIEGAND, Christopher J. ,  RAHMAN, Tofizur ,  OUELLETTE, Daniel G. ,  SMITH, Angeline K. ,  BROCKMAN, Justin S. ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOCZY, Mark L. ,  DOYLE, Brian S. ,  GOLONZKA, Oleg ,  ALZATE VINASCO, Juan G.

IPC: H01L43/10 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: A memory device includes a bottom electrode disposed above a substrate, a fixed magnet disposed above the bottom electrode, a tunnel barrier including a magnesium oxide disposed on the fixed magnet, a free magnet on the tunnel barrier, a cap oxide layer disposed on the free magnet, a follower magnet disposed on the oxide layer and a metallic cap disposed on the follower magnet. The metallic cap includes a metal such as Hf, W and Ta and further includes a trace amounts of an inert gas. One or more conductive nano-channels extend from the metallic cap through the free magnet and into the oxide layer, where each of the one or more conductive nano-channels include the material of the metallic cap. The memory device further includes an etch stop layer disposed on the metallic cap and a top electrode disposed on the etch stop layer.

公开(公告)号：WO2017111851A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/000421

申请日：2015-12-24

Applicant: INTEL CORPORATION ,  DOYLE, Brian, S. ,  KARPOV, Elijah, V. ,  OGUZ, Kaan ,  O'BRIEN, Kevin, P. ,  KUO, Charles, C. ,  DOCZY, Mark, L. ,  SHAH, Uday ,  WANG, Yih

Inventor： DOYLE, Brian, S. ,  KARPOV, Elijah, V. ,  OGUZ, Kaan ,  O'BRIEN, Kevin, P. ,  KUO, Charles, C. ,  DOCZY, Mark, L. ,  SHAH, Uday ,  WANG, Yih

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

Abstract: Memory cells with improved tunneling magnetoresistance ratio (TMR) are disclosed. In some embodiments such devices may include a magnetoresistive tunnel junction (MTJ) element coupled in series with a tunneling magnetoresistance enhancement element (TMRE). The MTJ element and TMRE may each be configured to transition between high and low resistance states, e.g., in response to a voltage. In some embodiments, the MTJ and TMRE are configure such that when a read voltage is applied to the cell while the MTJ is in its low resistance state the TMRE is driven to is low resistance state, and when such voltage is applied while the MTJ is in its high resistance state, the TMRE remains in its high resistance state. Devices and systems including such memory cells are also disclosed.

Abstract translation: 公开了具有改进的隧道磁阻比（TMR）的存储器单元。 在一些实施例中，这种器件可以包括与隧穿磁阻增强元件（TMRE）串联耦合的磁阻隧道结（MTJ）元件。 例如，响应于电压，MTJ元件和TMRE均可以被配置为在高电阻状态和低电阻状态之间转换。 在一些实施例中，MTJ和TMRE被配置为使得当在MTJ处于其低电阻状态时将读取电压施加到单元时，TMRE被驱动为低电阻状态，并且当MTJ是 在其高电阻状态下，TMRE保持高电阻状态。 包括这种存储器单元的器件和系统也被公开了。

公开(公告)号：WO2017052573A1

公开(公告)日：2017-03-30

申请号：PCT/US2015/052148

申请日：2015-09-25

Applicant: INTEL CORPORATION ,  KUO, Charles C. ,  SURI, Satyarth ,  OGUZ, Kaan ,  DOCZY, Mark L. ,  O'BRIEN, Kevin P. ,  DOYLE, Brian S.

Inventor： KUO, Charles C. ,  SURI, Satyarth ,  OGUZ, Kaan ,  DOCZY, Mark L. ,  O'BRIEN, Kevin P. ,  DOYLE, Brian S.

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for forming a step proximate an interface between a free magnetic layer and a dielectric layer of a magnetic tunnel junction. In some embodiments, the step may be defined by a spacer material, which may also serve to control the slope of the sidewalls of the dielectric layer and a fixed magnetic layer during the production of the device. As a result, an offset field exhibited by the STTM element may be reduced or even eliminated. Devices and systems including such STTM elements are also described.

Abstract translation: 公开了用于制造自旋转移转矩存储器（STTM）元件的技术。 在一些实施例中，技术包括用于形成靠近磁性隧道结的自由磁性层和电介质层之间的界面的台阶的方法。 在一些实施例中，该步骤可以由间隔物材料限定，间隔物材料也可以用于在制造装置期间控制电介质层的侧壁的斜率和固定的磁性层。 结果，可以减少或甚至消除由STTM元件展示的偏移场。 还描述了包括这种STTM元件的装置和系统。

公开(公告)号：WO2015147855A1

公开(公告)日：2015-10-01

申请号：PCT/US2014/032138

申请日：2014-03-28

Applicant: INTEL CORPORATION ,  KUO, Charles, C. ,  OGUZ, Kaan ,  DOYLE, Brian, S. ,  DOCZY, Mark, L. ,  KENCKE, David, L. ,  SURI, Satyarth ,  CHAU, Robert, S.

Inventor： KUO, Charles, C. ,  OGUZ, Kaan ,  DOYLE, Brian, S. ,  DOCZY, Mark, L. ,  KENCKE, David, L. ,  SURI, Satyarth ,  CHAU, Robert, S.

IPC: G11C11/16 ,  H01L29/82

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L43/12

Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.

Abstract translation: 公开了用于制造具有点接触自由磁性层的自对准自旋转移转矩存储器（STTM）装置的技术。 在一些实施例中，所公开的STTM装置包括覆盖导电硬掩模层的侧壁的第一介电间隔物，其被图案化以提供用于STTM自由磁性层的电子接触。 硬掩模接触可以比自由磁性层更窄。 第一介电间隔物可用于图案化STTM的固定磁性层。 在一些实施例中，STTM还包括覆盖其自由磁性层的侧壁的可选的第二电介质间隔物。 第二电介质间隔物可以用于图案化STTM的固定磁性层，并且可以至少部分地用于保护自由磁性层的侧壁在这种图案化期间重新沉积蚀刻副产物，从而防止固定磁性层 和自由磁性层。

公开(公告)号：WO2005067033A1

公开(公告)日：2005-07-21

申请号：PCT/US2004/043239

申请日：2004-12-21

Applicant: INTEL CORPORATION ,  KAVALIEROS, Jack ,  BRASK, Justin, K. ,  DOCZY, Mark, L. ,  HARELAND, Scott, A. ,  METZ, Matthew, V. ,  BARNS, Chris, E. ,  CHAU, Robert, S.

Inventor： KAVALIEROS, Jack ,  BRASK, Justin, K. ,  DOCZY, Mark, L. ,  HARELAND, Scott, A. ,  METZ, Matthew, V. ,  BARNS, Chris, E. ,  CHAU, Robert, S.

IPC: H01L21/8238

CPC classification number: H01L29/517 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/66545 ,  Y10S438/926

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate material, selectively removing the n-type gate material to form a recess in the first gate structure, and then filling the recess with an n-type metal gate material.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法包括提供包括包括n型栅极材料的第一晶体管结构和包括p型栅极材料的第二晶体管结构的衬底，选择性地去除n型栅极材料以在第一栅极结构中形成凹陷，然后 用n型金属栅极材料填充凹部。