公开(公告)号：WO2016048376A1

公开(公告)日：2016-03-31

申请号：PCT/US2014/057865

申请日：2014-09-26

Applicant: INTEL CORPORATION ,  DOCZY, Mark L. ,  OGUZ, Kaan ,  DOYLE, Brian S. ,  KUO, Charles C. ,  CHAU, Robert S. ,  SURI, Satyarth

Inventor： DOCZY, Mark L. ,  OGUZ, Kaan ,  DOYLE, Brian S. ,  KUO, Charles C. ,  CHAU, Robert S. ,  SURI, Satyarth

IPC: G11C11/16

CPC classification number: G11C11/161 ,  H01F10/3286 ,  H01L27/222 ,  H01L43/10 ,  H01L43/12

Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

Abstract translation: 一种用于磁隧道结的材料层堆叠，所述材料层堆叠包括固定的磁性层; 电介质层; 自由磁性层; 和非晶导电种子层，其中固定磁性层设置在电介质层和籽晶层之间。 一种非易失性存储器件，包括：包括非晶导电种子层的材料堆叠; 并且固定的磁性层并置并与种子层接触。 一种方法，包括在存储器件的第一电极上形成无定形晶种层; 在所述非晶种子层上形成材料层堆叠，所述材料堆叠包括设置在固定磁性层和自由磁性层之间的介电层，其中所述固定磁性层。

公开(公告)号：WO2015147813A1

公开(公告)日：2015-10-01

申请号：PCT/US2014/031854

申请日：2014-03-26

Applicant: INTEL CORPORATION ,  DOYLE, Brian, S. ,  KENCKE, David, L. ,  OGUZ, Kaan ,  DOCZY, Mark, L. ,  SURI, Satyarth ,  CHAU, Robert, S. ,  KUO, Charles, C. ,  GOLIZADEH MOJARAD, Roksana

Inventor： DOYLE, Brian, S. ,  KENCKE, David, L. ,  OGUZ, Kaan ,  DOCZY, Mark, L. ,  SURI, Satyarth ,  CHAU, Robert, S. ,  KUO, Charles, C. ,  GOLIZADEH MOJARAD, Roksana

IPC: H01L43/08 ,  H01L43/12 ,  G11C11/16

CPC classification number: G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Techniques are disclosed for forming a spin-transfer torque memory (STTM) element having an annular contact to reduce critical current requirements. The techniques reduce critical current requirements for a given magnetic tunnel junction (MTJ), because the annular contact reduces contact size and increases local current density, thereby reducing the current needed to switch the direction of the free magnetic layer of the MTJ. In some cases, the annular contact surrounds at least a portion of an insulator layer that prevents the passage of current. In such cases, current flows through the annular contact and around the insulator layer to increase the local current density before flowing through the free magnetic layer. The insulator layer may comprise a dielectric material, and in some cases, is a tunnel material, such as magnesium oxide (MgO). In some cases, a critical current reduction of at least 10% is achieved for a given MTJ.

Abstract translation: 公开了用于形成具有环形接触的自旋转移力矩存储器（STTM）元件以减少临界电流要求的技术。 该技术降低给定磁性隧道结（MTJ）的临界电流要求，因为环形接触可以减小接触尺寸并增加局部电流密度，从而减少切换MTJ自由磁性层方向所需的电流。 在一些情况下，环形触点围绕防止电流通过的绝缘体层的至少一部分。 在这种情况下，电流流过环形触点并且在绝缘体层周围流动，以在流过自由磁性层之前增加局部电流密度。 绝缘体层可以包括介电材料，并且在一些情况下，是隧道材料，例如氧化镁（MgO）。 在某些情况下，对于给定的MTJ，实现至少10％的临界电流降低。

公开(公告)号：WO2013154564A1

公开(公告)日：2013-10-17

申请号：PCT/US2012/033295

申请日：2012-04-12

Applicant: INTEL CORPORATION ,  KUO, Charles ,  KARPOV, Elijah, V. ,  DOYLE, Brian, S. ,  KENCKE, David, L. ,  CHAU, Robert, S.

Inventor： KUO, Charles ,  KARPOV, Elijah, V. ,  DOYLE, Brian, S. ,  KENCKE, David, L. ,  CHAU, Robert, S.

IPC: G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C11/15

CPC classification number: H01L43/10 ,  G11C5/025 ,  G11C5/063 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1659 ,  G11C13/003 ,  G11C2213/15 ,  G11C2213/71 ,  H01L43/12

Abstract: Techniques, materials, and circuitry are disclosed which enable low-voltage, embedded memory applications. In one example embodiment, an embedded memory is configured with a bitcell having a memory element and a selector element serially connected between an intersection of a wordline and bitline. The selector element can be implemented, for instance, with any number of crystalline materials that exhibit an S-shaped current-voltage (IV) curve, or that otherwise enables a snapback in the selector voltage after the threshold criteria is exceeded. The snapback of the selector is effectively exploited to accommodate the ON-state voltage of the selector under a given maximum supply voltage, wherein without the snapback, the ON-state voltage would exceed that maximum supply voltage. In some example embodiments, the maximum supply voltage is less than 1 volt (e.g., 0.9 volts or less).

Abstract translation: 公开了能够实现低电压嵌入式存储器应用的技术，材料和电路。 在一个示例实施例中，嵌入式存储器配置有具有存储元件的位单元和串行连接在字线和位线的交叉点之间的选择器元件。 选择器元件可以例如用任何数量的表现出S形电流 - 电压（IV）曲线的结晶材料来实现，或者否则在超过阈值标准之后能使得在选择器电压中的回跳。 选择器的快速恢复被有效地用于在给定的最大电源电压下适应选择器的导通状态电压，其中在没有快速恢复的情况下，导通状态电压将超过该最大供电电压。 在一些示例性实施例中，最大供电电压小于1伏特（例如，0.9伏或更小）。

公开(公告)号：WO2013101001A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067661

申请日：2011-12-28

Applicant: INTEL CORPORATION ,  MUKHERJEE, Niloy ,  METZ, Matthew V. ,  POWERS, James M. ,  LE, Van H. ,  CHU-KING, Benjamin ,  LEMAY, Mark R. ,  RADOSAVLJEVIC, Marko ,  GOEL, Niti ,  CHOW, Loren ,  TOLCHINSKY, Peter G. ,  KAVALIEROS, Jack T. ,  CHAU, Robert S.

Inventor： MUKHERJEE, Niloy ,  METZ, Matthew V. ,  POWERS, James M. ,  LE, Van H. ,  CHU-KING, Benjamin ,  LEMAY, Mark R. ,  RADOSAVLJEVIC, Marko ,  GOEL, Niti ,  CHOW, Loren ,  TOLCHINSKY, Peter G. ,  KAVALIEROS, Jack T. ,  CHAU, Robert S.

IPC: H01L21/20 ,  H01L29/778

CPC classification number: H01L29/06 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02587 ,  H01L21/0259 ,  H01L21/02617 ,  H01L21/02636 ,  H01L21/02658 ,  H01L21/02664

Abstract: Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.

Abstract translation: 描述了在非天然表面上形成具有降低的表面粗糙度和体缺陷密度的异质层以及由此形成的器件的方法。 在一个实施例中，该方法包括提供具有晶格常数的顶表面并在衬底的顶表面上沉积第一层的衬底。 第一层具有不同于衬底顶表面的第一晶格常数的晶格常数的顶表面。 第一层被退火和抛光以形成抛光表面。 然后在抛光表面上方沉积第二层。

公开(公告)号：WO2012125194A1

公开(公告)日：2012-09-20

申请号：PCT/US2011/063411

申请日：2011-12-06

Applicant: INTEL CORPORATION ,  DOYLE, Brian S. ,  KUO, Charles C. ,  LINDERT, Nick ,  SHAH, Uday ,  SURI, Satyarth ,  CHAU, Robert S.

Inventor： DOYLE, Brian S. ,  KUO, Charles C. ,  LINDERT, Nick ,  SHAH, Uday ,  SURI, Satyarth ,  CHAU, Robert S.

IPC: H01L27/108 ,  H01L21/8247

CPC classification number: H01L27/10894 ,  H01L27/10817 ,  H01L27/10855 ,  H01L28/91

Abstract: Semiconductor structures having integrated double-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded double-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A U-shaped metal plate is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the U-shaped metal plate. A top metal plate layer is disposed on and conformal with the second dielectric layer.

Abstract translation: 描述了具有用于eDRAM的集成双壁电容器的半导体结构及其形成方法。 例如，嵌入式双壁电容器包括设置在设置在基板上方的第一电介质层中的沟槽。 沟槽有一个底部和侧壁。 U形金属板设置在沟槽的底部，与侧壁间隔开。 第二电介质层设置在沟槽和U形金属板的侧壁上并与其一致。 顶部金属板层设置在第二介电层上并与第二介质层保形。

公开(公告)号：WO2012092038A2

公开(公告)日：2012-07-05

申请号：PCT/US2011/066271

申请日：2011-12-20

Applicant: INTEL CORPORATION ,  MUKHERJEE, Niloy ,  DEWEY, Gilbert ,  RADOSAVLJEVIC, Marko ,  CHAU, Robert S. ,  METZ, Matthew V.

Inventor： MUKHERJEE, Niloy ,  DEWEY, Gilbert ,  RADOSAVLJEVIC, Marko ,  CHAU, Robert S. ,  METZ, Matthew V.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28575 ,  H01L29/66446

Abstract: A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.

Abstract translation: 一般介绍通过在源极和漏极中使用III-V半导体中间层来减少n沟道晶体管的接触电阻的方法。 就此而言，引入包括具有源极区和漏极区的n型晶体管的器件，邻近晶体管的第一层间电介质层，穿过第一层间电介质层到源极区的沟槽以及位于源极区和源极区之间的导电源触点 沟槽，源极触点通过III-V半导体中间层与源极区域分开。 其他实施例也被公开和要求保护。

公开(公告)号：WO2011071598A3

公开(公告)日：2011-08-18

申请号：PCT/US2010053218

申请日：2010-10-19

Applicant: INTEL CORP ,  DEWEY GILBERT ,  CHAU ROBERT S ,  RADOSAVLJEVIC MARKO ,  METZ MATTHEW V ,  PILLARISETTY RAVI

Inventor： DEWEY GILBERT ,  CHAU ROBERT S ,  RADOSAVLJEVIC MARKO ,  METZ MATTHEW V ,  PILLARISETTY RAVI

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66666 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

Abstract: Quantum- well-based semiconductor devices and methods of forming quantum- well-based semiconductor devices are described. A method includes providing a hetero- structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

Abstract translation: 描述了基于量子阱的半导体器件和形成基于量子阱的半导体器件的方法。 一种方法包括提供设置在衬底上方并包括量子阱沟道区域的异质结构。 该方法还包括在量子阱沟道区上方形成源极和漏极材料区。 该方法还包括在源极和漏极材料区域中形成沟槽以提供与漏极区域分离的源极区域。 该方法还包括在源极和漏极区之间的沟槽中形成栅极介电层; 以及在栅极介电层上方的沟槽中形成栅电极。

公开(公告)号：WO2011087606A2

公开(公告)日：2011-07-21

申请号：PCT/US2010/058683

申请日：2010-12-02

Applicant: INTEL CORPORATION ,  PILLARISETTY, Ravi ,  KAVALIEROS, Jack, T. ,  CHU-KUNG, Benjamin ,  RACHMADY, Willy ,  HUDAIT, Mantu, K. ,  MUKHERJEE, Niloy ,  RADOSAVLJEVIC, Marko ,  CHAU, Robert, S.

Inventor： PILLARISETTY, Ravi ,  KAVALIEROS, Jack, T. ,  CHU-KUNG, Benjamin ,  RACHMADY, Willy ,  HUDAIT, Mantu, K. ,  MUKHERJEE, Niloy ,  RADOSAVLJEVIC, Marko ,  CHAU, Robert, S.

CPC classification number: H01L29/7784 ,  H01L29/151 ,  H01L29/155 ,  H01L29/201 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/78

Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

Abstract translation: 公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。 这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。 不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离 通过间隔材料。

公开(公告)号：WO2011071598A2

公开(公告)日：2011-06-16

申请号：PCT/US2010/053218

申请日：2010-10-19

Applicant: INTEL CORPORATION ,  DEWEY, Gilbert ,  CHAU, Robert S. ,  RADOSAVLJEVIC, Marko ,  METZ, Matthew V. ,  PILLARISETTY, Ravi

Inventor： DEWEY, Gilbert ,  CHAU, Robert S. ,  RADOSAVLJEVIC, Marko ,  METZ, Matthew V. ,  PILLARISETTY, Ravi

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66666 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

Abstract: Quantum- well-based semiconductor devices and methods of forming quantum- well-based semiconductor devices are described. A method includes providing a hetero- structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

Abstract translation: 描述了基于量子阱的半导体器件和形成量子阱基半导体器件的方法。 一种方法包括提供设置在衬底上方并包括量子阱沟道区的异质结构。 该方法还包括在量子阱沟道区上方形成源极和漏极材料区域。 该方法还包括在源极和漏极材料区域中形成沟槽以提供与漏极区域分离的源极区域。 该方法还包括在沟槽中，在源极和漏极区之间形成栅极电介质层; 以及在所述沟槽中形成栅电极，在所述栅介质层上方。

公开(公告)号：WO2010080276A2

公开(公告)日：2010-07-15

申请号：PCT/US2009066944

申请日：2009-12-07

Applicant: INTEL CORP ,  MUKHERJEE NILOY ,  DEWEY GILBERT ,  METZ MATTHEW V ,  KAVALIEROS JACK ,  CHAU ROBERT S

Inventor： MUKHERJEE NILOY ,  DEWEY GILBERT ,  METZ MATTHEW V ,  CHAU ROBERT S

IPC: H01L21/3205 ,  H01L21/28

CPC classification number: H01L29/517 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/0895 ,  H01L29/41791 ,  H01L29/452 ,  H01L29/456 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

Abstract translation: 与源极或漏极区的接触。 接触件具有导电材料，但是导电材料通过绝缘体与源极或漏极区域分离。