公开(公告)号：WO2006098820A2

公开(公告)日：2006-09-21

申请号：PCT/US2006/003531

申请日：2006-02-01

Applicant: FREESCALE SEMICONDUCTOR ,  GARCIA, Sam, S. ,  MICHAELSON, Lynne, M. ,  ACOSTA, Edward ,  CHATTERJEE, Ritwik ,  FILIPIAK, Stanley, M. ,  MATHEW, Varughese

Inventor： GARCIA, Sam, S. ,  MICHAELSON, Lynne, M. ,  ACOSTA, Edward ,  CHATTERJEE, Ritwik ,  FILIPIAK, Stanley, M. ,  MATHEW, Varughese

IPC: H01L21/4763

CPC classification number: H01L21/76849 ,  H01L21/76822 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76856

Abstract: A diffusion barrier stack is formed by forming a layer (30) comprising a metal over a conductor (26) that includes copper; and forming a first dielectric layer (32) over the layer (30), wherein the dielectric layer (32) is of a thickness that alone it can not serve as a diffusion barrier layer to the conductor and the first dielectric layer (32) prevents oxidation of the layer (30). In one embodiment, the diffusion barrier stack includes two layers; the first layer is a conductive layer (30) and the second layer is a dielectric layer (32). The diffusion barrier stack minimizes electromigration and copper diffusion from the conductor (26).

Abstract translation: 通过在包括铜的导体（26）上形成包括金属的层（30）形成扩散阻挡层叠体; 以及在所述层（30）上形成第一介电层（32），其中所述电介质层（32）的厚度单独地不能用作所述导体的扩散阻挡层，并且所述第一介电层（32）防止 层（30）的氧化。 在一个实施例中，扩散阻挡堆叠包括两层; 第一层是导电层（30），第二层是介电层（32）。 扩散阻挡层将导电体（26）的电迁移和铜扩散最小化。

公开(公告)号：WO2009088659A2

公开(公告)日：2009-07-16

申请号：PCT/US2008/086920

申请日：2008-12-16

Applicant: FREESCALE SEMICONDUCTOR INC. ,  MATHEW, Varughese ,  ACOSTA, Eddie ,  CHATTERJEE, Ritwik ,  GARCIA, Sam S.

Inventor： MATHEW, Varughese ,  ACOSTA, Eddie ,  CHATTERJEE, Ritwik ,  GARCIA, Sam S.

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L24/11 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A method forms a micropad (30, 70, 42) to an external contact (14, 54, 78) of a first semiconductor device (12, 52, 74). A stud (20, 24, 66, 88, 82) of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin (28) replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips.

Abstract translation: 一种方法形成到第一半导体器件（12,52,74）的外部触点（14,54,78）的微型焊盘（30,70,42）。 在外部触点上形成铜的螺柱（20,24,66,88,82）。 柱头在第一半导体器件的表面上方延伸。 铜的螺柱浸入锡溶液中。 锡（28）代替至少95％的螺柱铜，最好超过99％。 其结果是锡微珠的铜重量百分比低于5％。 由于微焊垫基本上是纯锡，所以在第一半导体器件的微焊盘未粘合的时间期间不会形成金属间键。 由于不形成金属间化合物，所以结果更小。 当第一半导体器件接合到覆盖的第二半导体器件时，接合尺寸不会显着增加堆叠芯片的高度。

公开(公告)号：WO2006098820A3

公开(公告)日：2007-04-26

申请号：PCT/US2006003531

申请日：2006-02-01

Applicant: FREESCALE SEMICONDUCTOR INC ,  GARCIA SAM S ,  MICHAELSON LYNNE M ,  ACOSTA EDWARD ,  CHATTERJEE RITWIK ,  FILIPIAK STANLEY M ,  MATHEW VARUGHESE

Inventor： GARCIA SAM S ,  MICHAELSON LYNNE M ,  ACOSTA EDWARD ,  CHATTERJEE RITWIK ,  FILIPIAK STANLEY M ,  MATHEW VARUGHESE

IPC: H01L23/48 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76849 ,  H01L21/76822 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76856

Abstract: A diffusion barrier stack is formed by forming a layer (30) comprising a metal over a conductor (26) that includes copper; and forming a first dielectric layer (32) over the layer (30), wherein the dielectric layer (32) is of a thickness that alone it can not serve as a diffusion barrier layer to the conductor and the first dielectric layer (32) prevents oxidation of the layer (30). In one embodiment, the diffusion barrier stack includes two layers; the first layer is a conductive layer (30) and the second layer is a dielectric layer (32). The diffusion barrier stack minimizes electromigration and copper diffusion from the conductor (26).

Abstract translation: 通过在包括铜的导体（26）上形成包括金属的层（30）形成扩散阻挡层叠体; 以及在所述层（30）上形成第一介电层（32），其中所述电介质层（32）的厚度单独地不能用作所述导体的扩散阻挡层，并且所述第一介电层（32）防止 层（30）的氧化。 在一个实施例中，扩散阻挡堆叠包括两层; 第一层是导电层（30），第二层是介电层（32）。 扩散阻挡层将导电体（26）的电迁移和铜扩散最小化。

公开(公告)号：WO2007024470A2

公开(公告)日：2007-03-01

申请号：PCT/US2006/030823

申请日：2006-08-08

Applicant: FREESCALE SEMICONDUCTOR ,  MARTIN, Gerald A. ,  GARCIA, Sam S. ,  MATHEW, Varughese

Inventor： MARTIN, Gerald A. ,  GARCIA, Sam S. ,  MATHEW, Varughese

IPC: H01L21/4763

CPC classification number: H01L21/76849 ,  H01L21/7684

Abstract: A method for making a semiconductor device includes forming a patterned dielectric (18) overlying active circuitry, the patterned dielectric having a plurality of cavities (15). A diffusion barrier (20) is formed over the patterned dielectric (18). A conductive layer (22) is formed over the diffusion barrier in the plurality of cavities. The conductive layer is etched back to be below a top surface of the dielectric, forming recessed areas (24) over the conductive layers in the plurality of cavities. The recessed areas are then filled with a capping film (26). The capping film and the diffusion barrier are removed to provide a relatively smooth planarized surface. Providing a relatively smooth planarized surface reduces leakage currents between conductors.

Abstract translation: 制造半导体器件的方法包括形成覆盖有源电路的图案化电介质（18），所述图案化电介质具有多个空腔（15）。 扩散势垒（20）形成在图案化电介质（18）上。 导电层（22）形成在多个空腔中的扩散阻挡层上。 导电层被回蚀到电介质的顶表面之下，在多个空腔中的导电层上形成凹陷区域（24）。 然后用封盖膜（26）填充凹进的区域。 去除覆盖膜和扩散阻挡层以提供相对光滑的平坦化表面。 提供相对平滑的平坦化表面减少导体之间的漏电流。

公开(公告)号：WO2006130222A1

公开(公告)日：2006-12-07

申请号：PCT/US2006/012236

申请日：2006-04-04

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  MATHEW, Varughese ,  ACOSTA, Edward ,  GARCIA, Sam S. ,  MICHAELSON, Lynne M.

Inventor： MATHEW, Varughese ,  ACOSTA, Edward ,  GARCIA, Sam S. ,  MICHAELSON, Lynne M.

IPC: H01L21/302

CPC classification number: H01L21/76849 ,  C11D3/2082 ,  C11D3/2086 ,  C11D3/3947 ,  C11D11/0047 ,  H01L21/02074

Abstract: A method (50) for making a semiconductor device (10) includes cleaning a semiconductor wafer after a chemical mechanical polishing (CMP) process to remove or reduce particles of copper, a corrosion inhibitor such as triazole, and a copper oxide layer on the copper layer (19). In order to prepare for plating the copper layer with a layer (26) that functions as a barrier to copper migration or diffusion, the surface of the copper layer and the dielectric layer (20) are treated with an oxidant, a surfactant, and copper-chelating agent. The copper-chelating is preferably a mild acid such as an organic acid. The oxidant is particularly useful in removing the corrosion inhibitor. The barrier layer (26), preferably conductive, is then plated on the surface of the copper layer (19). Subsequent interlayer dielectric layers and copper layers follow that can use the same process.

Abstract translation: 一种用于制造半导体器件（10）的方法（50）包括在化学机械抛光（CMP）工艺之后清洁半导体晶片以除去或减少铜的颗粒，诸如三唑的腐蚀抑制剂和铜上的氧化铜层 层（19）。 为了准备用作为铜迁移或扩散的屏障的层（26）对铜层进行电镀，铜层和电介质层（20）的表面用氧化剂，表面活性剂和铜 - 切割剂。 铜螯合物优选为弱酸，例如有机酸。 氧化剂特别适用于去除腐蚀抑制剂。 然后将优选导电的阻挡层（26）镀在铜层（19）的表面上。 随后的层间电介质层和铜层可以使用相同的工艺。

公开(公告)号：WO2009088659A3

公开(公告)日：2009-09-03

申请号：PCT/US2008086920

申请日：2008-12-16

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW VARUGHESE ,  ACOSTA EDDIE ,  CHATTERJEE RITWIK ,  GARCIA SAM S

Inventor： MATHEW VARUGHESE ,  ACOSTA EDDIE ,  CHATTERJEE RITWIK ,  GARCIA SAM S

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L24/11 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A method forms a micropad (30, 70, 42) to an external contact (14, 54, 78) of a first semiconductor device (12, 52, 74). A stud (20, 24, 66, 88, 82) of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin (28) replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips.

Abstract translation: 一种方法形成到第一半导体器件（12,52,74）的外部接触（14,54,78）的微突起（30,70,42）。 在外部触点上方形成铜钉（20,24,36,88,82）。 螺柱在第一半导体器件的表面之上延伸。 将铜柱浸入锡溶液中。 锡（28）代替至少95％的螺柱铜，优选超过99％。 结果是具有小于5重量％的铜的锡微粉末。 由于微电极基本上是纯锡，所以在第一半导体器件的微型焊盘未被接合的时间内，金属间键不会形成。 因为不形成金属间键，因此产生较小的微尺寸尺寸。 当第一半导体器件结合到上覆的第二半导体器件时，焊接尺寸不会显着增加堆叠芯片的高度。

公开(公告)号：WO2007024470A3

公开(公告)日：2007-09-27

申请号：PCT/US2006030823

申请日：2006-08-08

Applicant: FREESCALE SEMICONDUCTOR INC ,  MARTIN GERALD A ,  GARCIA SAM S ,  MATHEW VARUGHESE

Inventor： MARTIN GERALD A ,  GARCIA SAM S ,  MATHEW VARUGHESE

IPC: H01L21/4763

CPC classification number: H01L21/76849 ,  H01L21/7684

Abstract: A method for making a semiconductor device includes forming a patterned dielectric (18) overlying active circuitry, the patterned dielectric having a plurality of cavities (15). A diffusion barrier (20) is formed over the patterned dielectric (18). A conductive layer (22) is formed over the diffusion barrier in the plurality of cavities. The conductive layer is etched back to be below a top surface of the dielectric, forming recessed areas (24) over the conductive layers in the plurality of cavities. The recessed areas are then filled with a capping film (26). The capping film and the diffusion barrier are removed to provide a relatively smooth planarized surface. Providing a relatively smooth planarized surface reduces leakage currents between conductors.

Abstract translation: 一种用于制造半导体器件的方法包括形成覆盖有源电路的图案化电介质（18），该图案化电介质具有多个空腔（15）。 在图案化的电介质（18）上形成扩散阻挡层（20）。 导电层（22）形成在多个空腔中的扩散阻挡层上方。 将导电层回蚀至电介质的顶表面下方，在多个空腔中的导电层上方形成凹陷区域（24）。 然后用封盖膜（26）填充凹陷区域。 覆盖膜和扩散阻挡层被去除以提供相对平滑的平面化表面。 提供相对平滑的平面化表面可减少导体之间的泄漏电流。