公开(公告)号：WO2013148393A1

公开(公告)日：2013-10-03

申请号：PCT/US2013/032777

申请日：2013-03-18

Applicant: CYPRESS SEMICONDUCTOR CORPORATION ,  RAMKUMAR, Krishnaswamy ,  JENNE, Fredrick ,  LEVY, Sagy

Inventor： RAMKUMAR, Krishnaswamy ,  JENNE, Fredrick ,  LEVY, Sagy

IPC: H01L29/792

CPC classification number: H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7926

Abstract: An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.

Abstract translation: 描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。 通常，该方法包括：在衬底的第一区域中形成存储器件的通道，覆盖衬底表面的半导体材料，连接存储器件的源极和漏极的沟道; 在与所述通道的多个表面相邻的所述通道上形成电荷捕获电介质堆叠，其中所述电荷捕获电介质堆叠包括在隧道层上的电荷捕获层上的阻挡层; 以及在所述衬底的第二区域上形成MOS器件。

公开(公告)号：WO2008147383A1

公开(公告)日：2008-12-04

申请号：PCT/US2007/020956

申请日：2007-09-28

Applicant: CYPRESS SEMICONDUCTOR CORPORATION ,  POLISHCHUK, Igor ,  LEVY, Sagy ,  RAMKUMAR, Krishnaswamy

Inventor： POLISHCHUK, Igor ,  LEVY, Sagy ,  RAMKUMAR, Krishnaswamy

IPC: H01L21/336 ,  H01L21/00

CPC classification number: H01L29/792 ,  H01L21/28123 ,  H01L21/28167 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/045 ,  H01L29/42324

Abstract: A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region.

Abstract translation: 描述了一种非易失性电荷陷阱存储器件及其形成方法。 该器件包括具有<100>晶面取向的沟道长度的沟道区。 沟道区域位于一对源极区和漏极区之间，栅极堆叠设置在沟道区的上方。

公开(公告)号：WO2007092551A2

公开(公告)日：2007-08-16

申请号：PCT/US2007/003352

申请日：2007-02-07

Applicant: CYPRESS SEMICONDUCTOR CORPORATION ,  POLISHCHUK, Igor ,  RAMKUMAR, Krishnaswamy ,  LEVY, Sagy Levy

Inventor： POLISHCHUK, Igor ,  RAMKUMAR, Krishnaswamy ,  LEVY, Sagy Levy

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: In one embodiment, a self-aligned contact (SAC) trench structure (412) is formed through a dielectric layer (410) to expose an active region (404) of a MOS transistor. The SAC trench structure (412) not only exposes the active region (404) for electrical connection but also removes portions of a stress liner (409) over the active region (404). This leaves the stress liner (409) mostly on the sidewall and top of the gate (510) of the MOS transistor. Removing portions of the stress liner (409) over the active region substantially removes the lateral component of the strain imparted by the stress liner (409) on the substrate (402), allowing for improved drive current without substantially degrading a complementary MOS transistor.

Abstract translation: 在一个实施例中，自对准接触（SAC）沟槽结构（412）通过电介质层（410）形成以暴露MOS晶体管的有源区（404）。 SAC沟槽结构（412）不仅暴露用于电连接的有源区（404），而且还去除有源区（404）上的应力衬垫（409）的部分。 这使得应力衬垫（409）主要在MOS晶体管的栅极（510）的侧壁和顶部上。 在有源区上移除应力衬垫（409）的部分基本上去除了由衬底（402）上的应力衬垫（409）施加的应变的侧向分量，从而允许改进的驱动电流而不会使互补MOS晶体管基本上降级。

公开(公告)号：WO2014008166A1

公开(公告)日：2014-01-09

申请号：PCT/US2013/048885

申请日：2013-07-01

Applicant: CYPRESS SEMICONDUCTOR CORPORATION ,  POLISHCHUK, Igor ,  LEVY, Sagy ,  RAMKUMAR, Krishnaswamy

Inventor： POLISHCHUK, Igor ,  LEVY, Sagy ,  RAMKUMAR, Krishnaswamy

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

Abstract: A semiconductor devices including non-volatile memones and methods of fabricating the same to improve performance thereof are provided. Generally, the device includes a memory transistor comprising a polysilicon channel region electrically connecting a source region and a drain region formed in a substrate, an oxide-nitride-nitride- oxide (ONNO) stack disposed above the channel region, and a high work function gate electrode formed over a surface of the ONNO stack. In one embodiment the ONNO stack includes a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer. Other embodiments are also disclosed.

Abstract translation: 提供了包括非挥发性记忆体的半导体器件及其制造方法以提高其性能。 通常，该器件包括存储晶体管，其包括电连接形成在衬底中的源极区域和漏极区域的多晶硅沟道区域，设置在沟道区域上方的氧化物氮化物 - 氮化物氧化物（ONNO）堆叠以及高功函数 栅电极形成在ONNO堆的表面上。 在一个实施方案中，ONNO堆叠包括多层电荷捕获区域，其包括富含氧的第一氮化物层和设置在第一氮化物层上方的无氧的第二氮化物层。 还公开了其他实施例。

公开(公告)号：WO2014008157A1

公开(公告)日：2014-01-09

申请号：PCT/US2013/048870

申请日：2013-07-01

Applicant: CYPRESS SEMICONDUCTOR CORPORATION ,  LEVY, Sagy ,  JENNE, Fredrick ,  RAMKUMAR, Krishnaswamy

Inventor： LEVY, Sagy ,  JENNE, Fredrick ,  RAMKUMAR, Krishnaswamy

IPC: H01L29/792

CPC classification number: H01L29/792 ,  B82Y10/00 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02271 ,  H01L29/125 ,  H01L29/4234 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7926

Abstract: Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer. The multi-layer charge-trapping region includes a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer disposed above the first nitride layer.

Abstract translation: 缩放电荷俘获存储器件和由此制成的物品。 在一个实施例中，电荷俘获存储器件包括具有源极区，漏极区和电连接源极和漏极的沟道区的衬底。 隧道介电层设置在沟道区上方的衬底上方，以及设置在隧道介电层上的多层电荷俘获区。 多层电荷俘获区域包括设置在隧道电介质层上的第一氘化层，设置在第一氘化层上的第一氮化物层和设置在第一氮化物层上方的第二氮化物层。

公开(公告)号：WO2013148343A1

公开(公告)日：2013-10-03

申请号：PCT/US2013/032339

申请日：2013-03-15

Applicant: CYPRESS SEMICONDUCTOR CORPORATION ,  LEVY, Sagy ,  RAMKUMAR, Krishnaswamy ,  JENNE, Fredrick ,  GEHA, Sam

Inventor： LEVY, Sagy ,  RAMKUMAR, Krishnaswamy ,  JENNE, Fredrick ,  GEHA, Sam

IPC: H01L29/792

CPC classification number: H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66833 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7926

Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

Abstract translation: 描述了包括多层电荷存储层的半导体存储器件的实施例及其形成方法。 通常，该器件包括由半导体材料形成的通道，该半导体材料覆盖连接存储器件的源极和漏极的衬底上的表面; 覆盖通道的隧道氧化物层; 以及多层电荷存储层，其在所述隧道氧化物层上包含富氧的第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上无陷阱，并且将贫氧的第二氧氮化物层上 第一氧氮化物层，其中第二氧氮化物层的化学计量组成导致其陷阱致密。 在一个实施例中，该器件包括非平面晶体管，其包括具有邻接沟道的多个表面的栅极，并且栅极包括隧道氧化物层和多层电荷存储层。

公开(公告)号：WO2008147385A1

公开(公告)日：2008-12-04

申请号：PCT/US2007/020965

申请日：2007-09-28

Applicant: CYPRESS SEMICONDUCTRO CORPORATION ,  LEVY, Sagy ,  JENNE, Fredrick, B. ,  RAMKUMAR, Krishnaswamy

Inventor： LEVY, Sagy ,  JENNE, Fredrick, B. ,  RAMKUMAR, Krishnaswamy

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/66833

Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

Abstract translation: 描述了非易失性电荷陷阱存储器件。 该器件包括具有沟道区和一对源极/漏极区的衬底。 栅极堆叠在沟道区域上方之间以及在一对源极/漏极区域之间的衬底之上。 栅极堆叠包括具有第一氘化层的多层电荷捕获区域。 多层电荷俘获区域还可以包括不含氘的电荷俘获层。

公开(公告)号：WO2007092551A3

公开(公告)日：2007-12-13

申请号：PCT/US2007003352

申请日：2007-02-07

Applicant: CYPRESS SEMICONDUCTOR CORP ,  POLISHCHUK IGOR ,  RAMKUMAR KRISHNASWAMY ,  LEVY SAGY LEVY

Inventor： POLISHCHUK IGOR ,  RAMKUMAR KRISHNASWAMY ,  LEVY SAGY LEVY

IPC: H01L21/8238 ,  H01L21/461 ,  H01L29/94

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: In one embodiment, a self-aligned contact (SAC) trench structure (412) is formed through a dielectric layer (410) to expose an active region (404) of a MOS transistor. The SAC trench structure (412) not only exposes the active region (404) for electrical connection but also removes portions of a stress liner (409) over the active region (404). This leaves the stress liner (409) mostly on the sidewall and top of the gate (510) of the MOS transistor. Removing portions of the stress liner (409) over the active region substantially removes the lateral component of the strain imparted by the stress liner (409) on the substrate (402), allowing for improved drive current without substantially degrading a complementary MOS transistor.

Abstract translation: 在一个实施例中，通过介电层（410）形成自对准接触（SAC）沟槽结构（412）以暴露MOS晶体管的有源区（404）。 SAC沟槽结构（412）不仅暴露用于电连接的有源区（404），而且还移除有源区（404）上的应力衬垫（409）的部分。 这使应力衬垫（409）大部分留在MOS晶体管的栅极（510）的侧壁和顶部上。 去除有源区上方的应力衬里（409）的部分基本上去除了由衬底（402）上的应力衬里（409）施加的应变的横向分量，从而允许改进的驱动电流而基本不会使互补MOS晶体管退化。

公开(公告)号：WO2014008160A2

公开(公告)日：2014-01-09

申请号：PCT/US2013/048874

申请日：2013-07-01

Applicant: CYPRESS SEMICONDUCTOR CORPORATION ,  JENNE, Fredrick ,  LEVY, Sagy ,  RAMKUMAR, Krishnaswamy

Inventor： JENNE, Fredrick ,  LEVY, Sagy ,  RAMKUMAR, Krishnaswamy

IPC: H01L21/336 ,  H01L29/792

CPC classification number: H01L29/792 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3468 ,  G11C16/349 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7926

Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygenlean second layer.

Abstract translation: 提供了一种缩放非易失性俘获电荷存储器件及其制造的器件的方法。 在一个实施例中，该方法包括形成包括电连接衬底中的源极区域和漏极区域的多晶硅沟道区域。 通过氧化衬底以在沟道区域上的衬底上形成隧穿层以形成氧化膜并氮化氧化膜。 在隧道层上形成包含富氧的第一层和无氧的第二层的多层电荷俘获层，以及沉积在多层电荷俘获层上的阻挡层。 在一个实施方案中，该方法还包括稀释的湿氧化以致致密的沉积的阻塞氧化物并氧化一部分氧气第二层。

公开(公告)号：WO2008147386A1

公开(公告)日：2008-12-04

申请号：PCT/US2007/020966

申请日：2007-09-28

Applicant: CYPRESS SEMICONDUCTOR CORPORATION ,  JENNE, Fredrick, B. ,  LEVY, Sagy

Inventor： JENNE, Fredrick, B. ,  LEVY, Sagy

IPC: H01L21/31

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/3143 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518

Abstract: Scaling a nonvolatile trapped-charge memory device and the article made thereby. In an embodiment, scaling includes multiple oxidation and nitridation operations to provide a tunneling layer with a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. In an embodiment, scaling includes forming a charge trapping layer with a non-homogenous oxynitride stoichiometry. In one embodiment the charge trapping layer includes a silicon-rich, oxygen-rich layer and a silicon-rich, oxygen-lean oxynitride layer on the silicon-rich, oxygen-rich layer. In an embodiment, the method for scaling includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the silicon- rich, oxygen-lean oxynitride layer.

Abstract translation: 缩放非易失性捕获电荷存储器件及其制成的制品。 在一个实施例中，缩放包括多次氧化和氮化操作，以提供具有高于纯二氧化硅隧道层的介电常数的隧道层，但是具有比在衬底界面处具有氮的隧穿层更少的氢和氮阱。 在一个实施例中，缩放包括形成具有非均匀氧氮化物化学计量的电荷俘获层。 在一个实施方案中，电荷俘获层包含富含硅的富氧层和在富硅的富氧层上的富含氧的贫氧氧氮化物层。 在一个实施方案中，缩放方法包括稀释湿氧化以致密集沉积的阻塞氧化物并氧化一部分富含富含氧的氧氮化物层。