公开(公告)号：WO2010002515A3

公开(公告)日：2010-07-29

申请号：PCT/US2009044810

申请日：2009-05-21

Applicant: SOITEC SILICON ON INSULATOR ,  MAZURE CARLOS ,  NGUYEN BICH-YEN

Inventor： MAZURE CARLOS ,  NGUYEN BICH-YEN

IPC: H01L21/20

CPC classification number: H01L21/76251

Abstract: In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.

Abstract translation: 在一个实施例中，本发明提供了这样的基板，其被构造成使得在其顶层中制造的器件具有与在标准高电阻率基板中制造的相同器件类似的性质。 本发明的衬底包括具有标准电阻率的支撑体，布置在支撑衬底上的具有高电阻率，优选大于约1000欧姆 - 厘米的半导体层，布置在高电阻率层上的绝缘层，以及顶层 排列在绝缘层上。 本发明还提供了制造这种衬底的方法。

公开(公告)号：WO2010015401A2

公开(公告)日：2010-02-11

申请号：PCT/EP2009/005694

申请日：2009-08-06

Applicant: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES ,  LETERTRE, Fabrice ,  MAZURE, Carlos ,  KRAMES, Michael, R. ,  MCLAURIN, Melvin, B. ,  GARDNER, Nathan, F.

Inventor： LETERTRE, Fabrice ,  MAZURE, Carlos ,  KRAMES, Michael, R. ,  MCLAURIN, Melvin, B. ,  GARDNER, Nathan, F.

IPC: H01L21/324 ,  H01L21/20 ,  H01L33/00

CPC classification number: H01L21/2007 ,  H01L21/02422 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02658 ,  H01L21/3245 ,  H01L33/0095

Abstract: The present invention relates to a method for relaxing a strained material layer, comprising depositing a first low-viscosity layer comprising a first compliant material on the strained material layer, depositing a second low-viscosity layer comprising a second compliant material on the strained material layer to form a first sandwiched structure and subjecting the first sandwiched structure to a heat treatment such that reflow of the first and the second low-viscosity layers is caused thereby at least partly relaxing the strained material layer.

Abstract translation: 本发明涉及一种松弛应变材料层的方法，包括在应变材料层上沉积包含第一顺应材料的第一低粘度层，在应变材料层上沉积包含第二柔性材料的第二低粘度层 以形成第一夹层结构，并对第一夹层结构进行热处理，从而使第一和第二低粘度层的回流至少部分地松弛应变材料层。

公开(公告)号：WO2010002516A3

公开(公告)日：2010-01-07

申请号：PCT/US2009/044825

申请日：2009-05-21

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  NGUYEN, Bich-yen ,  MAZURE, Carlos

Inventor： NGUYEN, Bich-yen ,  MAZURE, Carlos

IPC: H01L21/20

Abstract: In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates.

公开(公告)号：WO2011107356A1

公开(公告)日：2011-09-09

申请号：PCT/EP2011/052421

申请日：2011-02-18

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  MAZURE, Carlos ,  FERRANT, Richard

Inventor： MAZURE, Carlos ,  FERRANT, Richard

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1203

Abstract: This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures.

Abstract translation: 本发明提供了一种半导体器件结构，其形成在常规的绝缘体上半导体（SeOI）衬底上，该衬底由限定至少一个场效应晶体管的图案限定，该场效应晶体管具有：在SeOI衬底的薄膜中，源极区， ，沟道区和形成在沟道区上方的前控制栅区; 以及位于所述SeOI衬底的所述掩埋氧化物之下的所述基底衬底中，所述背面控制栅极区域布置在所述沟道区域下方并且被配置为响应于偏压而移位所述晶体管的阈值电压。 本发明还提供了定义包括由本发明提供的FET图案的阵列的标准单元型电路结构和数据路径单元型电路结构的图案。 这种电路结构还包括连接背栅控制区的后栅极线。 本发明还提供了操作和设计这种半导体器件结构的方法。

公开(公告)号：WO2011107355A1

公开(公告)日：2011-09-09

申请号：PCT/EP2011/052413

申请日：2011-02-18

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  MAZURE, Carlos ,  FERRANT, Richard

Inventor： MAZURE, Carlos ,  FERRANT, Richard

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L29/78609 ,  H01L29/78648

Abstract: The invention provides a data-path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator (SeOI) substrate. The data-path cell includes an array of field-effect transistors, each transistor having a source region, a drain region and a channel region formed in the thin semiconductor layer of the SeOI substrate, and further having a front gate control region formed above the channel region. In particular, one or more transistors of the data-path cell further includes a back gate control region formed in the bulk substrate beneath the channel region and configured so as to modify the performance characteristics of the transistor in dependence on its state of bias. Also, an integrated circuit including one or more of the data-path cells and methods for designing or driving these data-path cells.

Abstract translation: 本发明提供一种特别适用于其环境的数据通道单元，用于在绝缘体上半导体（SeOI）衬底上制造的集成电路中。 数据通道单元包括场效应晶体管阵列，每个晶体管具有形成在SeOI衬底的薄半导体层中的源极区，漏极区和沟道区，并且还具有形成在栅极上的前栅极控制区 渠道区域。 特别地，数据通道单元的一个或多个晶体管还包括形成在沟道区下面的体衬底中的背栅极控制区域，并且被配置为根据其偏置状态来修改晶体管的性能特性。 而且，包括一个或多个数据路径单元的集成电路以及用于设计或驱动这些数据路径单元的方法。

公开(公告)号：WO2006103491A1

公开(公告)日：2006-10-05

申请号：PCT/IB2005/001136

申请日：2005-03-29

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  LETERTRE, Fabrice ,  MAZURE, Carlos

Inventor： LETERTRE, Fabrice ,  MAZURE, Carlos

IPC: H01L21/20 ,  H01L21/762

CPC classification number: H01L21/2007 ,  H01L21/76254

Abstract: The invention proposes a SOI-type multilayer structure (105), comprising a support layer (101), at least two working layers (103, 104) having different crystalline orientations, an insulating layer (102) extending over at least a portion of said support layer (101), characterized in that said insulating layer (102) extends over the whole surface of said support layer (101), so as to extend between said support layer (101) and said working layers (103, 104). A process for manufacturing such a structure (105) is also provided.

Abstract translation: 本发明提出了一种SOI型多层结构（105），其包括支撑层（101），至少两个具有不同晶体取向的工作层（103,104），绝缘层（102），其延伸至所述 支撑层（101），其特征在于，所述绝缘层（102）在所述支撑层（101）的整个表面上延伸，以在所述支撑层（101）和所述工作层（103,104）之间延伸。 还提供了一种制造这种结构（105）的方法。

公开(公告)号：WO2004044975A1

公开(公告)日：2004-05-27

申请号：PCT/EP2003/013697

申请日：2003-11-06

Applicant: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES ,  GHYSELEN, Bruno ,  RAYSSAC, Olivier ,  AULNETTE, Cécile ,  MAZURE, Carlos

Inventor： GHYSELEN, Bruno ,  RAYSSAC, Olivier ,  AULNETTE, Cécile ,  MAZURE, Carlos

IPC: H01L21/762

CPC classification number: H01L21/76254 ,  H01L21/76243 ,  H01L21/76259 ,  Y10S438/959 ,  Y10S438/977 ,  Y10S438/981

Abstract: The invention relates to a method of producing a semiconductor structure, the method comprising: - forming in a first semiconductor material substrate (30) a first dielectric area (32a-c) of a first dielectric material having a first thickness and a second dielectric area (34a-b) having a second thickness, - assembling said first substrate with a second semiconductor material substrate (40), - fracturing the portion of the substrate in which the weakened layer is produced, and- thinning one or both substrates.

Abstract translation: 本发明涉及一种制造半导体结构的方法，该方法包括：在第一半导体材料衬底（30）中形成具有第一厚度的第一介电材料的第一介电区域（32a-c）和第二介电区域 （34a-b）， - 第二半导体材料基板（40）组装所述第一基板， - 破坏其中产生弱化层的基板的部分，以及 - 使一个或两个基板变薄。

公开(公告)号：WO2003062507A3

公开(公告)日：2003-07-31

申请号：PCT/EP2003/000693

申请日：2003-01-21

Applicant: S.O.I.TEC SILICON INSULATOR TECHNOLOGIES ,  GHYSELEN, Bruno ,  LETERTRE, Fabrice ,  MAZURE, Carlos

Inventor： GHYSELEN, Bruno ,  LETERTRE, Fabrice ,  MAZURE, Carlos

IPC: C30B29/40

Abstract: The invention relates to a method for manufacturing a free-standing substrate made of monocrystalline semi-conductor material.This method is characterized by the following steps comprising: - transferring of a thin nucleation layer (5, 5') onto a support (7) by creating between the two a removable bonding interface (9) ;- growing by epitaxy on said thin nucleation layer (5, 5'), a microcrystalline layer (10) of material intended to comprise said substrate, until it attains a sufficient thickness to be free-standing, while preserving the removable character of the bonding interface (9) ; the coefficients of thermal expansion of the material of the thick layer (10) and of the support material (7) being chosen to be different from each other, such that at the time of cooling of the assembly, the stresses induced by differential thermal expansion between the support material (7) and that of the thick layer (10) causing the removal of said nucleation layer (5, 5') and said monocrystalline thick layer (10) from said support (7) at the level of said removable bonding interface (9).

公开(公告)号：WO2011123199A1

公开(公告)日：2011-10-06

申请号：PCT/US2011/025647

申请日：2011-02-22

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  MAZURE, Carlos ,  NGUYEN, Bich-Yen ,  SADAKA, Mariam

Inventor： MAZURE, Carlos ,  NGUYEN, Bich-Yen ,  SADAKA, Mariam

IPC: H01L27/06 ,  H01L21/822

CPC classification number: H01L27/0688 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/187 ,  H01L21/8221 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: Methods of forming semiconductor structures include transferring a portion (116a) of a donor structure to a processed semiconductor structure (102) that includes at least one non-planar surface. An amorphous film (144) may be formed over at least one non-planar surface of the bonded semiconductor structure, and the amorphous film may be planarized to form one or more planarized surfaces. Semiconductor structures include a bonded semiconductor structure having at least one non-planar surface, and an amorphous film disposed over the at least one non-planar surface. The bonded semiconductor structure may include a processed semiconductor structure and a portion of a single crystal donor structure attached to a non-planar surface of the processed semiconductor structure.

Abstract translation: 形成半导体结构的方法包括将施主结构的部分（116a）转移到包括至少一个非平面表面的经处理的半导体结构（102）。 可以在结合的半导体结构的至少一个非平面表面上形成非晶膜（144），并且非晶膜可以被平坦化以形成一个或多个平坦化表面。 半导体结构包括具有至少一个非平面表面的键合半导体结构和设置在所述至少一个非平面表面上的非晶膜。 键合的半导体结构可以包括处理的半导体结构和附接到处理的半导体结构的非平面表面的单晶体施主结构的一部分。

公开(公告)号：WO2010002516A2

公开(公告)日：2010-01-07

申请号：PCT/US2009044825

申请日：2009-05-21

Applicant: SOITEC SILICON ON INSULATOR ,  NGUYEN BICH-YEN ,  MAZURE CARLOS

Inventor： NGUYEN BICH-YEN ,  MAZURE CARLOS

IPC: H01L21/20

CPC classification number: H01L21/76254 ,  H01L21/76256

Abstract: In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates.

Abstract translation: 在优选实施例中，本发明提供了包括支撑件，布置在支撑件上的第一绝缘层，布置在第一绝缘层上的非单晶半导体层的衬底，布置在非单晶半导体层上的第二绝缘层， 结晶半导体层; 以及设置在第二绝缘层上的顶层。 此外，可以在顶层上形成第一栅电极，并且可以在非单晶半导体层中形成第二栅电极。 本发明还提供了制造这种基材的方法。